Ultra Ata/100; Ide Initialization; Sata Support - Intel SE7520JR2 Technical Manual

Intel® Server Board SE7520JR2
The BIOS initializes and supports ATAPI devices such as LS-120/240, CDROM, CD-RW and
DVD.
The BIOS initializes and supports S-ATA devices just like P-ATA devices. It initializes the
embedded the IDE controllers in the chipset and any S-ATA devices that are connected to these
controllers. From a software standpoint, S-ATA controllers present the same register interface
as the P-ATA controllers. Hot plugging of S-ATA drives during the boot process is not supported
by the BIOS and may result in undefined behavior.
3.4.5.1

Ultra ATA/100

The IDE interfaces of the ICH5R DMA protocol redefines signals on the IDE cable to allow both
host and target throttling of data and transfer rates of up to 100MB/s.
3.4.5.2

IDE Initialization

The BIOS supports the ATA/ATAPI Specification, version 6 or later. The BIOS initializes the
embedded IDE controller in the chipset (ICH5-R) and the IDE devices that are connected to
these devices. The BIOS scans the IDE devices and programs the controller and the devices
with their optimum timings. The IDE disk read/write services that are provided by the BIOS use
PIO mode, but the BIOS programs the necessary Ultra DMA registers in the IDE controller so
that the operating system can use the Ultra DMA Modes.
3.4.6

SATA Support

The integrated Serial ATA (SATA) controller of the ICH5-R provides two SATA ports on the
baseboard. The SATA ports can be enabled/disabled and/or configured by accessing the BIOS
Setup Utility during POST.
The SATA function in the ICH5-R has dual modes of operation to support different operating
system conditions. In the case of native IDE-enabled operating systems, the ICH5-R has
separate PCI functions for serial and parallel ATA. To support legacy operating systems, there
is only one PCI function for both the serial and parallel ATA ports. The MAP register provides
the ability to share PCI functions. When sharing is enabled, all decode of I/O is done through
the SATA registers. A software write to the Function Disable Register (D31, F0, offset F2h, bit 1)
causes Device 31, Function 1 (IDE controller) to hidden, and its configuration registers are not
used. The SATA Capability Pointer Register (offset 34h) will change to indicate that MSI is not
supported in combined mode.
The ICH5-R SATA controller features two sets of interface signals that can be independently
enabled or disabled. Each interface is supported by an independent DMA controller. The ICH5-
R SATA controller interacts with an attached mass storage device through a register interface
that is equivalent to that presented by a traditional IDE host adapter. The host software follows
existing standards and conventions when accessing the register interface and follows standard
command protocol conventions.
SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer
rates will operate at the bus's maximum speed, regardless of the UDMA mode reported by the
SATA device or the system BIOS.
Revision 1.0
C78844-002
Functional Architecture
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