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® Intel Server Board SE7520JR2 Technical Product Specification Revision 1.0 October 2004 Enterprise Platforms and Services Marketing...
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Date Revision Number December 2003 June 2004 October 2004 Revision History Modifications Preliminary Release Memory Sub-system rewrite, BIOS Chapter Updated, Management Chapter re-write, Error Handling chapter re-write, several changes made to better reflect final design First non-NDA release; Updated IRQ routing diagrams, Updated mBMC Sensor tables, Updates to Regulatory Information, Updated Sensor data tables C78844-002...
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The Intel® Server Board SE7520JR2 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Baseboard Management Controller (mBMC) Core EPS for IPMI-based Systems • Sahalee Core BMC EPS for IPMI v1.5 These documents are not publicly available and must be ordered by your local Intel representative. Chapter Outline This document is divided into the following chapters •...
Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the...
1U and 2U server markets. Server Board SE7520JR2 SKU Availability In this document, the name SE7520JR2 is used to describe the family of boards that are made available under a common product name. The core features for each board will be common;...
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Light-Guided Diagnostics on all FRU devices (processors, memory, power) • Port-80 Diagnostic LEDs displaying POST codes The following figure shows the board layout of the Server Board SE7520JR2. Each connector and major component is identified by number and is identified in Table 1. C78844-002...
USB Port 1 Video Connector NIC #2 NIC #1 RJ-45 Serial B Port Stacked PS/2 Keyboard and Mouse Ports Intel Management Module Connector CMOS Battery Full Height Riser Card Slot Low Profile Riser Card Slot DIMM Slots 68-pin SCSI Channel A Connector LSI 53C1030 SCSI Controller MCH –...
Intel® Server Board SE7520JR2 Server Board Overview The following mechanical drawing shows the physical dimensions of the baseboard. Figure 2. Server Board Dimensions Revision 1.0 C78844-002...
This chapter provides a high-level description of the functionality associated with the architectural blocks that make up the Intel Server Board SE7520JR2. Note: This document describes the features and functionality of the Server Board SE7520JR2 when using standard on-board platform instrumentation. Some functionality and feature descriptions change when using either the Professional Edition or Advanced Edition Intel Management Modules.
Flexible Mother Board (FMB) specification for all 800 MHz FSB Intel Xeon processors. FMB is an estimation of the maximum values the 800 MHz FSB versions of the Intel Xeon processors will have over their lifetime. The value is only an estimate and actual specifications for future processors may differ.
® Note: Only Intel Xeon™ processors that support an 800MHz Front Side Bus are supported on the Server Board SE7520JR2. See the following table for a list of supported processors and their operating frequencies. Processor Family Intel® Xeon™...
Processor Family Intel® Xeon™ Intel® Xeon™ Intel® Xeon™ 3.1.6.1 Processor Mis-population Detection The processors must be populated in the correct order for the processor front-side bus to be correctly terminated. CPU socket 1 must be populated before CPU socket 2. Baseboard logic will prevent the system from powering up if a single processor is present but it is not in the correct socket.
3.1.6.7 Microcode IA-32 processors have the capability of correcting specific errata through the loading of an Intel- supplied data block (i.e., microcode update). The BIOS is responsible for storing the update in non-volatile memory and loading it into each processor during POST. The BIOS allows a number of microcode updates to be stored in the flash, limited by the amount of free space available.
3.1.9 Processor Thermal Control Sensor The Intel Xeon processors generate a signal to indicate throttling due to a processor over temp condition. The mBMC implements an IPMI sensor that provides the percentage of time a processor has been throttled over the last 1.46 seconds. Baseboard management forces a thermal control condition when reliable system operation requires reduced power consumption.
The following sub-sections provide an overview of the primary functions and supported features of each chipset component as they are used on the Server Board SE7520JR2. Later sections in this chapter provide more detail on the implementation of the sub-systems.
For conventional PCI Mode, the PXH supports PCI bus frequencies of 66 MHz, 100 MHz, and 133 MHz. On the Server Board SE7520JR2 each of the two PCI-X interfaces (PCI Bus A and PCI Bus B) is independently controlled to operate in either a conventional PCI or PCI-X mode. PCI Bus A is...
5-V tolerant, except PME#. The ICH5 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH5 requests. On the Server Board SE7520JR2 this PCI interface is used to support on-board PCI devices including the ATI* video controller, Super I/O chip, and hardware monitoring sub-system.
IDE channels of the ICH5R. One channel is accessed through the 40-pin connector on the baseboard. The signals of the second channel are routed to the 100-pin backplane connector for use in either the Intel Server Chassis SR1400 or SR2400 when integrated with a backplane for slim-line optical drive use.
USB 2.0 allows data transfers up to 480 Mb/s, which is 40 times faster than full-speed USB. The ICH5-R also contains four Universal Host Controller Interface (UHCI) controllers that support USB full-speed and low-speed signaling. On the Server Board SE7520JR2, the ICH5-R provides six USB 2.0 ports. All six ports are high-speed, full-speed, and low-speed capable.
DIMM is a single load device, ie) Single Rank = 1 Load. Dual rank DIMMs are dual load devices, ie) Dual Rank = 2 loads. The Server Board SE7520JR2 provides the following maximum memory capacities based on the number of DIMM slots provided and maximum supported memory loads by the chipset: •...
For double-sided DIMMs, both rows are said to be present. The Server Board SE7520JR2 has six DIMM slots, or three DIMM banks. Both DIMMs in a bank should be identical (same manufacturer, CAS latency, number of rows, columns and devices, timing parameters etc.).
Using the following algorithm, BIOS configures the memory controller of the MCH to run in either dual channel mode or single channel mode: (1) If 1 or more fully populated DIMM banks are detected, the memory controller is set to dual channel mode.
Table 5: Supported DDR2-400 DIMM Populations Bank 3 – DIMMs 3A, 3B Note: On the Server Board SE7520JR2, when using all dual rank DDR-333 or DDR2-400 DIMMs, a total of four DIMMs can be populated. Configuring more than four dual rank DDR- 333 or DDR2-400 DIMMs will result in the BIOS generating a memory configuration error.
status of the extended memory test is displayed on the console. The status of base and extended memory tests are also displayed on an LCD control panel if present. The extended memory test is configured using the BIOS Setup Utility. The coverage of the test can be configured to one of the following: •...
3.3.6.2 Integrated Memory Scrub Engine The Intel E7520 MCH includes an integrated engine to walk the populated memory space proactively seeking out soft errors in the memory subsystem. In the case of a single bit correctable error, this hardware detects, logs, and corrects the data except when an incoming write to the same memory address is detected.
3.3.6.3 Retry on Uncorrectable Error The Intel E7520 MCH includes specialized hardware to resubmit a memory read request upon detection of an uncorrectable error. When a demand fetch (as opposed to a scrub) of memory encounters an uncorrectable error as determined by the enabled ECC algorithm, the memory control hardware will cause a (single) full resubmission of the entire cache line request from memory to verify the existence of corrupt data.
3.3.6.5 DIMM Sparing Function To provide a more fault tolerant system, the Intel E7520 MCH includes specialized hardware to support fail-over to a spare DIMM device in the event that a primary DIMM in use exceeds a specified threshold of runtime errors. One of the DIMMs installed per channel, greater than or equal in size than all installed, will not be used but kept in reserve.
Mirroring is supported on dual-channel DIMM populations symmetric both across channels and within each channel. As a result, on the Server Board SE7520JR2 there are two supported configurations for memory mirroring: •...
Figure 7. Six DIMM Memory Mirror Configuration (DDR2 Only) These symmetry requirements are a side effect of the hardware mechanism for maintaining two copies of all main memory data while ensuring that each channel has a full copy of all data in preparation for fail-down to single-channel operation.
This section describes the function of each I/O interface and how they operate on the Server Board SE7520JR2. 3.4.1 PCI Subsystem The primary I/O interface for the Server Board SE7520JR2 is PCI, with four independent PCI bus segments. • A PCI 33MHz/32-bit bus segment (P32-A) is controlled through the ICH5-R.
3.4.1.4 PCI Riser Slots The Server Board SE7520JR2 has two riser slots capable of supporting riser cards for both 1U and 2U system configurations. Because of board placement resulting in different pin orientations, and expanded technology support associated with the full-height riser, the riser slots are proprietary and require different riser cards.
8 PCI-Express card, or two x 4 PCI-Express cards. Intel makes available a 1U single slot x8 riser card and a 2U three slot riser card which provides two x8 connectors each supporting x4 data widths. The third slot is a PCI-X slot. Using a baseboard configured with an integrated SCSI controller, the PCI-X add-in slot is capable of supporting a bus speed of up to 100MHz.
Functional Architecture Intel® Server Board SE7520JR2 hierarchical PCI bus under the current bridge. The PCI bus number and the subordinate PCI bus number are the same in the last hierarchical bridge. 3.4.1.7 Device Number and IDSEL Mapping Each device under a PCI bridge has its IDSEL input connected to one bit out of the PCI bus address/data signals AD[31::11] for the PCI bus.
The option ROM space is also used by the console redirection binary (if enabled) and the user binary (if present and configured for runtime usage). The SE7520JR2 BIOS integrates option ROMs for the Intel® 82546GB, the ATI* Rage XL, and the LSI* 53C1030 SCSI controller.
For APIC mode, the Server Board SE7520JR2 interrupt architecture incorporates three Intel I/O APIC devices to manage and broadcast interrupts to local APICs in each processor. The Intel I/O APICs monitor each interrupt on each PCI device including PCI slots in addition to the ISA compatibility interrupts IRQ(0-15).
3.4.3.3 Legacy Interrupt Sources The table below recommends the logical interrupt mapping of interrupt sources on the Server Board SE7520JR2. The actual interrupt map is defined using configuration registers in the ICH5-R. Interrupt IRQ0 Timer/counter, HPET #0 in legacy replacement Mode. In APIC mode, cascade from 8259 controller #1...
The IRQ / data frame structure includes the ability to handle up to 32 sampling channels with the standard implementation using the minimum 17 sampling channels. The Server Board SE7520JR2 has an external PCI interrupt serializer for PCIIRQ scan mechanism of ICH5-R to support 16 PCIIRQs.
Super I/O Timer Keyboard Cascade Serial Serial Floppy/IS SCI/ISA Mouse/IS Coprocessor P_IDE/IS Not Used USB 1.1 Controller #1 and #4 Video USB 1.1 Controller #3, Native IDE and SATA USB 1.1 Controller #2 Option for SCI, TCO, HPET#0,1,2 Option for SCI, TCO, HPET#0,1,2 Option for SCI, TCO, HPET#0,1,2 USB 2.0 EHCI Controller #1, Option for SCI, TCO, HPET#0,1,2...
3.4.4 SCSI Support The SCSI sub-system consists of the LSI 53C1030 Dual Channel Ultra320 SCSI controller, one internal 80-pin connector (SCSI Channel A), one external high 80-pin density SCSI connector (SCSI channel B), and on-board termination for both SCSI channels. 3.4.4.1 LSI* 53C1030 Dual Channel Ultra320 SCSI Controller The LSI53C1030 is a PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller that...
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• Quick arbitrate and select (QAS) • Skew compensation • Inter-symbol interference (ISI) compensation • Cyclic redundancy check (CRC) • Domain validation technology The LSI53C1030 contains the following SCSI performance features: • Supports Ultra320 SCSI • Paced transfers using a free running clock •...
RUBI2 standard. It will not have support for zero channel RAID cards that follow the RADIOS standard. See the SE7520JR2 Tested Hardware and OS list for a list of supported ZCR cards. Zero channel RAID (ZCR) capabilities enable the LSI 53C1030 to respond to accesses from a PCI RAID controller card or chip that is able to generate ZCR cycles.
The BIOS initializes and supports ATAPI devices such as LS-120/240, CDROM, CD-RW and DVD. The BIOS initializes and supports S-ATA devices just like P-ATA devices. It initializes the embedded the IDE controllers in the chipset and any S-ATA devices that are connected to these controllers.
The Intel RAID Technology for SATA Option ROM provides a pre-OS user interface for the Intel RAID Technology implementation and provides the ability for an Intel RAID Technology volume to be used as a boot disk as well as to detect any faults in the Intel RAID Technology volume(s) attached to the Intel RAID controller.
Requests are serviced in a manner that ensures display integrity and maximum CPU/coprocessor drawing performance. The Server Board SE7520JR2 supports an 8MB (512Kx32bitx4 Banks) SDRAM device for video memory. The following table shows the video memory interface signals:...
3.4.8 Network Interface Controller (NIC) The Intel 82546GB dual-channel gigabit network interface controller supplies the baseboard with two network interfaces. The 82546GB is a highly integrated PCI LAN controller in a 21 mm PBGA package. Each channel is capable of supporting 10/100/1000 operation and alert-on-LAN functionality.
• Wake up control 3.4.10.1 GPIOs The National Semiconductor* PC87427 Super I/O provides nine general-purpose input/output pins that the Server Board SE7520JR2 utilizes. The following table identifies the pin and the signal name used in the schematic: GPIO00/CLKRUN_L GPIO01/KBCLK GPIO02/KBDAT...
3.4.10.2.3 Serial Port Multiplexer Logic The Server Board SE7520JR2 has a multiplexer to connect the rear RJ45 connector to either Serial Port A or Serial Port B. This facilitates the routing of Serial Port A to the rear RJ45 connector if Serial Port B is used for Serial Over LAN (SOL). This serial port selection can be done through the BIOS setup option.
Serial B Serial A 3.4.10.2.4 Rear RJ45 Serial B Port Configuration The rear RJ45 Serial B port is a fully functional serial port that can support any standard serial device. Using an RJ45 connector for a serial port gives direct support for serial port concentrators, which are widely used in the high-density server market.
2MB programmable. The flash ROM contains system initialization routines, setup utility, and runtime support routines. The exact layout is subject to change, as determined by Intel. A 128- KB block is available for storing OEM code (user binary) and custom logos.
3.5.1 Memory Space At the highest level, the Intel Xeon processor address space is divided into four regions, as shown in the following figure. Each region contains the sub-regions that are described in following sections. Attributes can be independently assigned to regions and sub-regions using registers.
3.5.1.1 DOS Compatibility Region The first region of memory below 1 MB was defined for early PCs, and must be maintained for compatibility reasons. The region is divided into sub-regions as shown in the following figure. 0FFFFFh System BIOS 0F0000h 0EFFFFh Extended System BIOS...
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3.5.1.1.1 DOS Area The DOS region is 512 KB in the address range 0 to 07FFFFh. This region is fixed and all accesses go to main memory. 3.5.1.1.2 ISA Window Memory The ISA Window Memory is 128 KB between the address of 080000h to 09FFFFh. This area can be mapped to the PCI bus or main memory.
3.5.1.2 Extended Memory Extended memory is defined as all address space greater than 1MB. Extended Memory region covers 8GB maximum of address space from addresses 0100000h to FFFFFFFh, as shown in the following figure. PCI memory space can be remapped to top of memory (TOM). Extended lntel E7520 chipset region...
3.5.1.2.1 Main Memory All installed memory greater than 1MB is mapped to local main memory, up to 8GB of physical memory. Memory between 1MB to 15MB is considered to be standard ISA extended memory. 1MB of memory starting at 15MB can be optionally mapped to the PCI bus memory space. The remainder of this space, up to 8GB, is always mapped to main memory, unless TBSG SMM is used which is just under TOLM.
System Management RAM (SMRAM) provides code and data storage space for the SMI_L handler code, and is made visible to the processor only on entry to SMM, or other conditions that can be configured using Intel Lindenhurst PF chipset. The MCH supports three SMM options: •...
PC-compatible I/O devices and functions, which are mapped to specific addresses in I/O space. On SE7520JR2, the ICH5-R provides the bridge to ISA functions. The I/O map in the following table shows the location in I/O space of all direct I/O-accessible registers.
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Address (es) 0071h RTC Data 0073h RTC Data 0075h RTC Data 0077h RTC Data 0080h – 0081h BIOS Timer 0080h – 008F DMA Low Page Register 0090h – 0091h DMA Low Page Register (aliased) 0092h System Control Port A (PC-AT control Port) (this port not aliased in DMA range) 0093h –...
Parallel Port (ECP) 07BCh – 07Beh Parallel Port (ECP) 0CF8h PCI CONFIG_ADDRESS Register 0CF9h Intel® Server Board SE7520JR2 Turbo and Reset Control 0CFCh PCI CONFIG_DATA Register 3.5.3 Accessing Configuration Space All PCI devices contain PCI configuration space, accessed using mechanism #1 defined in the PCI Local Bus Specification.
3.5.3.1 CONFIG_ADDRESS Register CONFIG_ADDRESS is 32 bits wide and contains the field format shown in the following figure. Bits [23::16] choose a specific bus in the system. Bits [15::11] choose a specific device on the selected bus. Bits [10:8] choose a specific function in a multi-function device. Bit [7::1] select a specific register in the configuration space of the selected device or function on the bus.
IA-32 Core – The IA-32 core contains standard services and components such as the PCI Resource manager, ACPI support, POST, and runtime functionality. • Manageability Extensions – Intel servers build server management into the BIOS through the Intelligent Platform Management Interface (IPMI) and baseboard management hardware.
The flash ROM contains system initialization routines, the BIOS Setup Utility, and runtime support routines. The exact layout is subject to change, as determined by Intel. A 64-KB user block is available for user ROM code or custom logos. The flash ROM also contains initialization code in compressed form for onboard peripherals, like SCSI, NIC and video controllers.
4.3.1.1 System Activity Window The top row of the screen is reserved for the system state window. On a graphics console, the window is 640x48. On a text console, the window is 80x2. The system state window may be in one of three forms, either an activity bar that scrolls while the system is busy, a progress bar that measures percent complete for the current task, or an attention required bar.
<Esc> key while in Quiet Boot mode. If Quiet Boot is disabled, the BIOS displays diagnostic messages in place of the activity indicator and the splash screen. With the use of an Intel supplied utility, the BIOS allows OEMs to override the standard Intel logo with one of their own design 4.3.1.3...
Please select boot device: Floppy Hard Drives ATAPI CDROM LAN PXE EFI Boot Manager ↓and↑ to move selection Enter to select boot device ESC to boot using defaults BIOS Setup Utility The BIOS Setup utility is provided to perform system configuration changes and to display current settings and environment information.
Option ↔ Select Menu The left and right arrow keys are used to move between the major menu pages. The keys have no affect if a sub-menu or pick list is displayed. Select Field The Tab key is used to move between fields. For example, Tab can be used to move from hours to minutes in the time item in the main menu.
Feature Options System Overview AMI BIOS Version Build Date Processor Type Speed Count System Memory Size System Time HH:MM:SS System Date DAY MM/DD/YYYY Language English French German Italian Spanish 4.4.2.2 Advanced Menu Table 20: BIOS Setup, Advanced Menu Options Feature Options Advanced Settings WARNING: Setting wrong values in below sections may cause system to malfunction.
Disabled Enabled Max CPUID Value Limit Disabled Enabled Hyper-Threading Technology Disabled Enabled Intel ® Speed Step ™ Tech Auto Disabled Revision 1.0 Options Help Text If enabled, all processors will be activated and retested on the next boot. This option will be automatically reset to disabled on the next boot.
Feature Options Third IDE Master Fourth IDE Master Hard Disk Write Disabled Protect Enabled IDE Detect Time Out (Sec) ATA(PI) 80Pin Cable Host & Device Detection Host Device Table 23: Mixed P-ATA-S-ATA Configuration with only Primary P-ATA Feature Options Mixed P-ATA / S-ATA First ATA P-ATA M-S Channel...
Allows BIOS to Select Serial Port A Base Addresses. Allows BIOS to Select Serial Port B Base Addresses. C78844-002 Description Note: Intel no longer validates 720Kb & 2.88Mb drives. Description Option that is used by other serial port is hidden to prevent conflicting settings.
4.4.2.2.5 USB Configuration Sub-menu Table 27: BIOS Setup, USB Configuration Sub-menu Selections Feature Options USB Configuration USB Devices Enabled USB Function Disabled Enabled Legacy USB Support Disabled Keyboard only Auto Keyboard and Mouse Port 60/64 Emulation Disabled Enabled USB 2.0 Controller Disabled Enabled USB 2.0 Controller...
Feature Options Device #n Emulation Type Auto Floppy Forced FDD Hard Disk CDROM 4.4.2.2.6 PCI Configuration Sub-menu This sub-menu provides control over PCI devices and their option ROMs. If the BIOS is reporting POST error 146, use this menu to disable option ROMs that are not required to boot the system.
Feature Options Slot 1 Option ROM Disabled Enabled Slot 2 Option ROM Disabled Enabled Slot 3 Option ROM Disabled Enabled Slot 4 Option ROM Disabled Enabled Slot 5 Option ROM Disabled Enabled Slot 6 Option ROM Disabled Enabled 4.4.2.2.7 Memory Configuration Sub-menu This sub-menu provides information about the DIMMs detected by the BIOS.
4.4.2.3.1 Boot Settings Configuration Sub-menu Selections Table 32: BIOS Setup, Boot Settings Configuration Sub-menu Selections Feature Options Boot Settings Configuration Quick Boot Disabled Enabled Quiet Boot Disabled Enabled (this is conflict with previous words in this doc. Based on my memory, it is enabled by default)
4.4.2.3.2 Boot Device Priority Sub-menu Selections Table 33: BIOS Setup, Boot Device Priority Sub-menu Selections Feature Options Boot Device Priority 1st Boot Device Varies Specifies the boot sequence from the available devices. A device enclosed in parenthesis has been disabled in the corresponding type menu.
nth Drive Varies Specifies the boot sequence from the available devices. 4.4.2.4 Security Menu Table 37: BIOS Setup, Security Menu Options Feature Options Security Settings Administrator Password is User Password is Set Admin Password Set User Password User Access Level No Access View Only Limited...
This node is grayed out if a user password is not installed. This node is grayed out if a user password is not installed. This node is hidden if the Intel Management Module is not present. This node is grayed out if a user password is not installed.
B selects UARTB. Help Text Setting this to Enabled will clear the System Event Log during the next boot. C78844-002 Description When the Intel Management Module is present, the help text directs the user to select Serial B for Serial Over LAN.
The active partition from which the system boots shall be referred to as the primary partition. The AMI FLASH update suite and Intel Online updates preserve the existing BIOS image on the primary partition. BIOS updates are diverted to the secondary partition. After the update is complete, a notification flag is set.
When a request is detected, the BIOS loads the default system configuration values during the next POST. In systems configured with an Intel Management Module, the CMOS can be cleared without opening the chassis. Using the control panel, the user can hold the reset button for 4 seconds and then press the power button while still pressing the reset button.
System software can locate a run-time user binary by searching for it like an option ROM. The system vendor can place a signature within the user binary to distinguish it from other option ROMs. Refer to the SE7520JR2 BIOS EPS for further details.
Operating Model The following table summarizes the operation of security features supported by the BIOS. Some security features require the Intel Management Module (IMM) to be installed. These include “Diskette Write Protect”, “Video Blanking”, and “Power Switch inhibit.” Table 43: Security Features Operating Model...
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Administrator/User Passwords and F2 Setup Usage Model Notes: • Visible=option string is active and changeable • Hidden=option string is inactive and not visible • Shaded=option string is gray-out and view-only There are three possible password scenarios: Scenario #1 Administrator Password Is Not Installed User Password Is Not Installed...
Get System Boot Options Command, takes appropriate action, and clears these settings. 4.9.1 Microsoft* Windows* Compatibility Intel Corporation and Microsoft Corporation co-author design guides for system designers using ® Intel processors and Microsoft* operating systems. These documents are updated yearly to address new requirements and current trends.
Intel® Server Board SE7520JR2 System BIOS PC200x specifications are intended for systems that are designed to work with Windows 2000* and Windows XP* class operating systems. The Hardware Design Guide (HDG) for the Windows XP platform is intended for systems that are designed to work with Windows XP class operating systems.
The BIOS supports a control panel sleep button. The sleep button may not be provided on all control panel designs. On systems where the sleep button is optional, a system configuration option will be provided to enable or disable the sleep button. The ACPI tables will be updated to indicate the presence or absence of the sleep button.
4.9.2.6 Sleep to On (ACPI) If an operating system is loaded, the sleep button generates a wake event to the ACPI chipset and a request (via SCI) to the OS to place the system in the “On” state. The OS retains control of the system and OS policy determines what sleep state (if any) and sleep sources the system can wake from.
4.10 PXE BIOS Support The BIOS will support PXE-compliant implementations that: • Locate and configure all PXE-capable boot devices (UNDI Option ROMs) in the system, both built-in and add-ins. • Supply a PXE according to the specification if the system includes a built-in network device. •...
IPMB. Through the redirection capabilities of the BMC on Intel® platforms, this serial port UART input/output stream is further redirected and sent over a platform LAN device as a packetized serial-byte stream. This BMC function is called Serial over LAN, or SOL, and further optimizes space requirements and server management capability.
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Sahalee BMC. If a described feature or function is unique, the specific management controller will be referenced. On-Board Platform Instrumentation Limited Limited Errors Only C78844-002 Intel® Intel® Management Management Module - Module - Professional Advanced Edition Edition Revision 1.0...
5.1.1 5V Standby The power supply must provide a 5V Standby power source for the platform to provide any management functionality. 5V Standby is a low power 5V supply that is active whenever the system is plugged into AC power. 5V Standby is used by the following onboard management devices: •...
Intel® Server Board SE7520JR2 Platform Management 5.1.3 IPMI ‘Sensor Model’ An IPMI-compatible ‘Sensor Model’ is used to unify the way that temperature, voltage, and other platform management status and control is represented and accessed. The implementation of this model is done according to command and data formats defined in the Intelligent Platform Management Interface Specification.
Management Controllers At the heart of platform management is a management controller. To support the tiered management model, the Server Board SE7520JR2 supports two different management controllers, the PC87431M mini-Baseboard Management Controller (mBMC) from National Semiconductor* and Intel’s Sahalee BMC. The Professional and Advanced modules electrically replace the mBMC with the more full featured ‘Sahalee’...
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• FRU Information Access. FRU (Field Replaceable Unit) information is non-volatile storage for serial number, part number, asset tag and other inventory information for the baseboard and chassis. The FRU implementation on SE7520JR2 includes write support for OEM-specific records. •...
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• Platform Event Filtering (PEF) • Keyboard Controller Style (KCS) IPMI-System Interface (Professional and Advanced systems only) • SMBus IPMI-System Interface (On-board Platform Instrumentation systems only) • Intelligent Chassis Management Bus (ICMB) support (Professional and Advanced systems only) • Remote Boot Control •...
Intel® Server Board SE7520JR2 Platform Management On-Board Platform Management Features and Functionality The National Semiconductor PC87431M mini-Baseboard Management Controller (mBMC) is an Application Specific Integrated Circuit (ASIC) with a Reduced Instruction Set Computer (RISC)- based processor and many peripheral devices embedded into it. It is targeted for a wide range of remote-controlled platforms, such as servers, workstations, hubs, and printers.
5.2.1 Server Management I The table below describes the server management I that are connected to the indicated bus. The column labeled “I physical I C bus connected to the mBMC. Only the Peripheral SMBus is available for use with the Write-Read I C IPMI command.
Intel® Server Board SE7520JR2 Platform Management Figure 21. External Interfaces to mBMC mBMC Hardware Architecture The following figure shows an example of the internal functional modules of the mBMC in a block diagram. The mBMC controls various server management functions, such as the system power/reset control, a variety of types of sensor monitoring, system initialization, fault resilient booting (FRB).
Platform Management Intel® Server Board SE7520JR2 Figure 22. mBMC Block Diagram 5.3.1 Power Supply Interface Signals The mBMC supports two power supply control signals: Power On and Power Good. The Power On signal connects to the chassis power subsystem through the chipset and is used to request power state changes (asserted = request Power On).
The following figure shows the power supply control signals and their sources. To turn on the system, the mBMC asserts the Power On signal and waits for the Power Good signal to assert in response, indicating that DC power is on. Figure 23.
5.3.2 Power Control Sources The sources listed in the following table can initiate power-up and/or power-down activity. Source Power button Front control power button mBMC Watchdog Timer Internal mBMC timer Platform Event Filtering Command Routed through command processor Power state retention Implemented via mBMC internal logic 5.3.3 Power-up Sequence...
RSTOUT output if Control Panel Lockout is disabled. The “Control Panel Reset Button pressed” event is logged in the SEL. The Intel® Local Control Panel with LCD, is not supported with on-board platform management. Either an IMM Professional Editaion or Advanced Edition must be installed to support this chassis option.
• Combined power and reset button assertion If DC power is off, an assertion of the PWBTIN while the RSTIN is asserted generates an OEM-specific Control Panel event to PEF. The event attributes are: Sensor Type code - 14h (Button) and Sensor Specific offset - 07h. This PEF action initiates a BIOS CMOS clear request to the system BIOS.
5.3.5.4.2 Fault / Status LED The following table shows mapping of sensors/faults to the LED state. Color Condition Solid System ready Green Blink System ready, but degraded: CPU disabled Solid Critical failure: critical fan, voltage, or temperature state Amber Blink Non-critical failure: non-critical fan, voltage, or temperature state Solid System not ready: POST error / NMI event / CPU or terminator missing...
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5.3.5.5.1 Chassis Intrusion Some platforms support chassis intrusion detection. On those platforms, the mBMC monitors chassis intrusion by polling the server input/output (SIO) device. The state of the chassis intrusion input is provided by the status register of the SIO device. A Chassis Intrusion event is logged in the System Event Log when a change in the input state is detected.
The mBMC supports a maximum SEL size of 92 entries. If an Intel® Management Module is installed in the server, the mBMC System Event Log is not accessible and is replaced by the Intel Management Module System Event Log.
The mBMC supports both low-going and high-going sensor devices. If an Intel Management Module is installed in the server, the mBMC SDRs are not accessible and are replaced by the Intel Management Module SDRs.
5.3.12 Field Replaceable Unit (FRU) Inventory Devices An enterprise-class system typically has FRU information for each major system board, (processor board, memory board, I/O board, etc.). The FRU data includes information such as serial number, part number, model, and asset tag. This information can be accessed in two ways: through IPMI FRU commands or by using Master Write-Read commands.
5.3.16 mBMC Self Test The mBMC performs various tests as part of its initialization. If a failure is determined (e.g., corrupt mBMC FRU, SDR, or SEL), the mBMC stores the error internally. 5.3.17 Messaging Interfaces This section describes the supported mBMC communication interfaces: •...
• SMBus data signal (SDAH) • Optional SMBus alert signal (SMBAH). The signal notifies the host that the PC87431x has data to provide. When the system main power is off (PWRGD signal is low), the host interface signals are in TRI-STATE to perform “passive”...
LAN Channel Capability Privilege Levels Authentication Types Number of LAN Alert Destinations Address Resolution Protocol (ARP) 5.3.18 Event Filtering and Alerting The mBMC implements most of the IPMI 1.5 alerting features. The following features are supported: • • Alert over LAN 5.3.18.1 Platform Event Filtering (PEF) The mBMC monitors platform health and logs failure events into the SEL.
down, power cycle, and/or reset actions, the actions are performed according to PEF Action Priorities. Note: An action that has changed from delayed to non-delayed, or an action whose delay time has been reduced automatically has higher priority. The mBMC can be configured to log PEF actions as SEL events.
mBMC sensors 01h – 08h are internal sensors to the mBMC and are used for event generation only. These sensors are not for use with the ‘Get Sensor Reading’ IPMI command and may return an error when read. Table 55: Platform Sensors for On-Board Platform Instrumentation Sensor Name Sensor Type Physical...
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Intel® Server Board SE7520JR2 Sensor Sensor Name Type Physical Physical Security Security Violation Voltage CPU1 12v Voltage CPU2 12v Voltage BB +1.5V Voltage BB +1.8V Voltage BB +3.3V Voltage BB +5V Voltage BB +12V Voltage BB -12V Voltage FSB Vtt...
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As & De Threshold [u,l][ c,nc] As & De Threshold [u,l][ c,nc] As & De Generic State Asserted As & De C78844-002 Intel® Server Board SE7520JR2 Readable Event Data Value/Offsets Action Fault LED Analog R, T Action Fault LED Analog...
The following tables are for the built-in and the external sensors for the platform when either an Intel Management Module Professional or Advanced is installed. Table 56. Platform Sensors for Intel Management Modules - Professional and Advanced Sensor Sensor Name...
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Intel® Server Board SE7520JR2 Sensor Sensor Name Sensor Type Number Critical Inerrupt Critical Interrupt Sensor Memory Memory Event Logging Event Logging Disabled Disabled Session Audit Session Audit Voltage BB +1.2V Vtt BB+1.2V Voltage NIC Core Voltage BB +1.5V BB +1.8V...
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Lags Digital Performance Met Discrete As & De or Lags Digital Performance Met Discrete As & De or Lags C78844-002 Intel® Server Board SE7520JR2 Readable Value / EventData Offsets Analog R, T Analog R, T Analog R, T Analog...
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Intel® Server Board SE7520JR2 Sensor Sensor Name Sensor Type Number Digital Fan 10 Digital Fan 11 LVDS SCSI Terminator channel 1 terminator fault LVDS SCSI Terminator channel 2 terminator fault Power Supply Power Supply Status 1 Power Supply Power Supply...
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Specific Entity Present IERR Thermal Trip FRB1, FRB2, Sensor FRB3 Specific As & De Config Error Presence Disabled C78844-002 Intel® Server Board SE7520JR2 Readable Value / EventData Offsets – Trig Offset – Trig Offset – Trig Offset – Trig Offset –...
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Intel® Server Board SE7520JR2 Sensor Sensor Name Sensor Type Number Processor 2 Processor Status Processor 1 Core Temp Temp Processor 2 Core Temp Temp Processor 1 12v Voltage Processor 2 12v Voltage Processor 1 Temp Thermal Control Processor 2 Temp...
Using SMBIOS, a system administrator can obtain the types, capabilities, operational status, installation date and other information about the system components. Refer to the SE7520JR2 BIOS EPS for detail describing access methods to the SMBIOS structure tables. Event /...
IPMI watchdog timer to protect against BIOS hangs during the POST process On systems that have an Intel Management Module installed, several different levels of FRB are supported: FRB1, FRB2, FRB3, and OS Watchdog Timer. The FRB algorithms detect BSP failures and take steps to disable that processor and reset the system so another processor will run as the BSP.
The first timer (FRB3) starts counting down whenever the system comes out of hard reset. With no Intel® Management Module, only one watchdog timer is present. If the BSP successfully resets and begins executing, the BIOS disables the FRB-3 timer in the BMC and the system continues executing POST.
6.1.5 AP Failures In systems configured with an Intel Management Module, the BIOS and Sahalee BMC implement additional safeguards to detect and disable the application processors (AP) in a multiprocessor system. If an AP fails to complete initialization within a certain time, it is assumed to be nonfunctional.
does not alter the BSP and attempts to boot from the original BSP. Error messages are displayed on the console, and errors are logged in the event log of a processor failure. If the user replaces a processor that has been marked bad by the system, the system must be informed about this change by running BIOS Setup and selecting that processor to be retested.
The following table shows memory error handling with both a mBMC and Sahalee BMC. Table 57: Memory Error Handling mBMC vs Sahalee Memory with RAS Server with mBMC mode Sparing mode / When Sparing or Mirroring occurs: Mirroring mode - BIOS will not report memory RAS configuration to mBMC.
In non-RAS mode, BIOS will assert a Non-Maskable-Interrupt (NMI) on the first Double Bit ECC (DBE) error. Table 58: Memory Error Handling in non-RAS mode Non-RAS mode Server with mBMC Single Bit ECC SBE error events will not be (SBE) errors logged.
Error Logging This section defines how errors are handled by the system BIOS. Also discussed is the role of the BIOS in error handling and the interaction between the BIOS, platform hardware, and server management firmware with regard to error handling. In addition, error-logging techniques are described and beep codes for errors are defined.
6.3.4 Memory Bus Error The hardware is programmed to generate an SMI on single-bit data errors in the memory array if ECC memory is installed. The SMI handler records the error and the DIMM location to the system event log. Double-bit errors in the memory array are mapped to the SMI because the mBMC cannot determine the location of the bad DIMM.
Gate20 Error Multi-Bit ECC Error Parity Error Message Displayed Boot Failure ... Invalid Boot Diskette Drive Not Ready A: Drive Error B: Drive Error Insert BOOT diskette in A: Reboot and Select proper Boot device or Insert Boot Media in selected Boot device NO ROM BASIC Table 61: Storage Device BIOS Messages Message Displayed...
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Message Displayed Primary Slave Hard Disk Error Secondary Master Hard Disk Error Secondary Slave Hard Disk Error Master Hard Disk Error Slave Hard Disk Error Master Hard Disk Error Slave Hard Disk Error Master Hard Disk Error Slave Hard Disk Error Master Hard Disk Error Slave Hard Disk Error Primary Master Drive - ATAPI Incompatible...
EPROM). BIOS could not find or load the CPU Microcode Update to the CPU. This message only applies to INTEL CPUs. The message is most likely to appear when a brand new CPU is installed in a motherboard with an outdated BIOS.
Halt: The message is displayed on the screen, an error is logged to the SEL, and the system cannot boot unless the error is corrected. The error codes are defined by Intel and whenever possible are backward compatible with error codes used on earlier platforms.
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Error Code 0012 CMOS time not set 0014 PS2 Mouse not found 0040 Refresh timer test failed 0041 Display memory test failed 0042 CMOS Display Type Wrong 0043 ~<INS> Pressed 0044 DMA Controller Error 0045 DMA-1 Error 0046 DMA-2 Error 0047 Unknown BIOS error.
Table 71: Troubleshooting BIOS Beep Codes Number of Beeps 1, 2 or 3 Reseat the memory, or replace with known good modules. 4-7, 9-11 Fatal error indicating a serious problem with the system. Consult your system manufacturer. Before declaring the motherboard beyond all hope, eliminate the possibility of interference by a malfunctioning add-in card.
Code Front panel CMOS clear initiated 1-5-1-1 FRB failure (processor failure) 1-5-2-1 No processors installed or processor socket 1 is empty. 1-5-2-3 Processor configuration error (e.g., mismatched VIDs, Processor slot 1 is empty) 1-5-2-4 Front-side bus select configuration error (e.g., mismatched BSELs) 1-5-4-2 Power fault: DC power unexpectedly lost (e.g.
Result Amber Diagnostic LEDs Figure 24. Location of Diagnostic LEDs on Baseboard 6.5.3 POST Code Checkpoints Diagnostic LED Decoder Checkpoint G=Green, R=Red, A=Amber Green Table 75: POST Code Checkpoints Disable NMI, parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Run-time data area. Initialize BIOS modules on POST entry and GPNV area.
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Diagnostic LED Decoder Checkpoint G=Green, R=Red, A=Amber Revision 1.0 Re-enable cache for boot strap processor Early CPU Init Exit Initializes the 8042 compatible Key Board Controller. Detects the presence of PS/2 mouse. Detects the presence of Keyboard in KBC port. Testing and initialization of different Input Devices.
Diagnostic LED Decoder Checkpoint G=Green, R=Red, A=Amber 6.5.4 Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS: Table 76: Bootblock Initialization Code Checkpoints Diagnostic LED Decoder Checkpoint...
Diagnostic LED Decoder Checkpoint G=Green, R=Red, A=Amber 6.5.5 Bootblock Recovery Code Checkpoint The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS: Table 77: Bootblock Recovery Code Checkpoint...
Diagnostic LED Decoder Checkpoint G=Green, R=Red, A=Amber 6.5.6 DIM Code Checkpoints The Device Initialization Manager (DIM) module gets control at various times during BIOS POST to initialize different Buses. The following table describes the main checkpoints where the DIM module is accessed: Checkpoint Initialize different buses and perform the following functions: Reset, Detect, and Disable (function 0).
6.5.8 POST Progress FIFO (Professional / Advanced only) With SE7520JR2 based platforms that utilize either the Professional or Advanced management modules, the Sahalee BMC will maintain a RAM FIFO of the last 16 post progress codes that it has received. Accompanying this FIFO is a timestamp that indicates when the last code was received.
Connectors and Jumper Blocks Power Connectors The main power supply connection is obtained using a SSI Compliant 2x12 pin connector. In addition, there are three additional power related connectors; one SSI compliant 2x4 pin power connector (J4J1) providing support for additional 12V, one SSI compliant 1x5 pin connector (J1G1) providing I C monitoring of the power supply, and one 1x2 pin IDE power connector (U2E1) providing power to support IDE flash devices.
The baseboard provides two riser slots; one providing PCI-X signals to a riser capable of supporting Low Profile add-in cards, and the other implementing Intel® Adaptive Slot Technology providing both PCI-X and PCI-Express signals to risers capable of supporting full height add-in cards.
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Pin- PCI Spec Description Side Signal INTB# This pin will be connected on the 2U riser to INT_B# of the bottom PCI slot, INT_A# of the middle slot and INT_D# of the top slot. INTD# This pin will be used by 1U/2U riser to bring the INT_D# interrupt on the bottom PCI slot down to the baseboard.
7.2.2 Full Height PCI-X Riser Slot The full-height/length riser slot is implemented using a 280-pin connector and utilizes Intel Adaptive Slot Technology capable of supporting both PCI-X and PCI-Express riser cards. On a given riser card, the PCI add-in slot closest to the baseboard will always have device ID 17. On a three-slot riser card the middle PCI add-in slot will have device ID 18, and the top slot will have device ID 19.
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Pin-Side PCI Spec Description Signal HSOn(7) INTB# This pin will be connected on the 2U riser to INT_B# of the bottom PCI slot, INT_A# of the middle slot and INT_D# of the top slot. INTD# This pin will be used by 1U/2U riser to bring the INT_B# interrupt from the top and INT_C# from the middle PCI...
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Pin-Side PCI Spec Description Signal +3.3V Was Vio 3.3V or 1.5V PME2# active riser only, PME needed per PCI segment, reserved for passive riser AD[31] AD[29] Ground AD[27] AD[25] +3.3V C/BE[3]# AD[23] Ground AD[21] AD[19] +3.3V AD[17] C/BE[2]# Ground IRDY# +3.3V DEVSEL# PCI-XCAP...
The baseboard provides several access points to the management buses built into the baseboard. The following table provides the pinouts for each connector. 7.3.1 Intel® Management Module Connector A 120-pin connector (J1C1) is included on the baseboard to support the optionally installed “Professional” or “Advanced” Management modules.
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FMC Signal Name FML_SINTEX FML_MDA_I2CSDA ICH_LCLK USB_M FMM_SYSIRQ USB_P ICH_LAD1 FMM_RSMRST_N ICH_LFRAME_N ICH_LAD0 ICH_LAD3 ICH_LPCPD_N ICH_LAD2 FMM_LPCRST_N DFP_CLK DFP_DAT IPMB_I2C_5VSB_SDA IPMB_I2C_5VSB_SCL SMB_I2C_3VSB_SDA SMB_I2C_3VSB_SCL PERIPH_I2C_3VSB_SDA PERIPH_I2C_3VSB_SCL MCH_I2C_3V_SDA MCH_I2C_3V_SCL LAN_I2C_3VSB_SDA Revision 1.0 Description Fast Management Link Slave Interrupt/Clock Extension. This signal is driven by the FML Slave, and has a dual usage: Used as an Alert signal for the slave to notify master that data is ready to be read from slave...
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FMC Signal Name LAN_I2C_3VSB_SCL HDD_FLT_LED_N FMM_PS_PWR_ON_N COOL_FLT_LED_N FMM_CPU_VRD_EN FMM_SCI_N ICH_PWR_BTN_N FMM_SPKR_N FP_NMI_BTN_N FP_SLP_BTN_N FP_ID_BTN_N SYS_PWR_GD CPU2_SKTOCC_N CLK_32K_RTC CPU1_SKTOCC_N FMM_SOUT FMM_SIN FMM_DCD_N FMM_RTS_N FMM_DTR_N FMM_CTS_N ICMB_RX ICMB_TX ICMB_TX_EN Description LAN usage Drive Fault LED output driven when FMM detects a bad drive from the Hot Swap controller on the Hot Swap disk Drive sub-system.
FMC Signal Name FMM_RI_BUF_N RST_PWRGD_PS LAN_SMBALERT_N ICH_SLP_S4_N ICH_SMI_BUFF_N CHPSET_ERR_ALERT_N FP_RST_BTN_N ICH_RST_BTN_N FP_PWR_BTN_N FMM_IRQ_SMI_N FMM_PRES_N 7.3.2 ICMB Header A white 5-pin header (J1D1) located on the left side of the baseboard near the internal SCSI connector cutout. 7.3.3 IPMB Header When either the “Professional” or “Advanced” management modules are installed, the yellow 3- pin IPMB connector (J3F1) can be used to access the IPMB bus.
Table 89: IPMB Connector Pin-out (J3F1) Local I2C SDA Local I2C SCL Signal Name Description BMC IMB 5 V STNDBY Data Line BMC IMB 5 V STNDBY Clock Line C78844-002 Revision 1.0...
The Server Board SE7520JR2 provides three control panel interconnects: a high density 100- pin connector for use in the Intel Server Chassis SR1400 1U and SR2400 2U with backplane installed, a 50-pin control panel connector used in Intel’s chassis with no backplane installed, and a SSI standard 34-pin connector for use in third-party reference chassis.
Figure 25. 34-Pin SSI Compliant Control Panel Header I/O Connectors 7.5.1 VGA Connector The following table details the pin-out definition of the VGA connector. Control Panel Pinout Power LED Cool Fault HDD LED System Fault Power Button LAN A Link / A Reset Button SMBus Intruder...
7.5.2 NIC Connectors The Server Board SE7520JR2 provides two RJ45 NIC connectors oriented side by side on the back edge of the board. The pin-out for each connector is identical and is defined in the following table: Table 95: RJ-45 10/100/1000 NIC Connector Pin-out 7.5.3...
7.5.4 ATA-100 Connector The Server Board SE7520JR2 provides one legacy ATA-100 40-pin connector (J3K1). The pin- out is defined in the following table. Its signals are not tied to the ATA functionality embedded into the high-density 100-pin front panel connector. Each connector is configured to a separate ATA port embedded in the ICH5-R.
7.5.5 SATA Connectors The Server Board SE7520JR2 provides two SATA (Serial ATA) connectors: SATA-0 (J1H1) and SATA-1 (J1H5), for use with an internal SATA backplane. The pin configuration for each connector is identical and is defined in the following table.
Table 99: Legacy 34-pin Floppy Drive Connector Pin-out (J3K2) 7.5.7 Serial Port Connectors The Server Board SE7520JR2 provides one external RJ45 Serial B port and one internal 9-pin Serial A header. The following tables define the pinouts for each. Table 100: External RJ-45 Serial B Port Pin-out...
7.5.8 Keyboard and Mouse Connector Two stacked PS/2 ports are provided to support both a keyboard and a mouse. Either PS/2 port can support a mouse or keyboard. The following table details the pin-out of the PS/2 connector. Table 102: Stacked PS/2 Keyboard and Mouse Port Pin-out 7.5.9 USB Connector The following table details the pin-out of the external USB connectors found on the back edge of...
One internal 1x10 connector on the baseboard (J1F1) provides an option to support an additional two USB 2.0 ports. This connector is used in both the Intel Server Chassis SR1400 1U and SR2400 2U bringing USB support to the control panel. The pin-out of the connector is detailed in the following table.
SDR package according to which system configuration is used. The 2x12 fan header (J3K6) is used to control system fans in both the Intel Server Chassis SR1400 and SR2400. The pinout for this connector is found in the following table.
BB_FAN_LED6_R The 1x3 fan header (J3K3) is used to control a system fan in the Intel Server Chassis SR1400. The pinout for this connector is found in the following table. Table 108: 3-Pin Fan Speed Controlled Fan Header (J3K3) Signal Name...
Jumper Blocks The baseboard has several jumper blocks used to configure or enable/disable various features. This section describes the usage and settings of each. Reference Name J1H2 (A) CMOS Clear Clears CMOS settings J1H2 (B) BIOS Forces the system to boot into BIOS Recovery Boot Recovery mode.
Design and Environmental Specifications Server Board SE7520JR2 Design Specification Operation of the Server Board SE7520JR2 at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability.
Note: The following diagram shows the power harness spec drawing as defined for use in Intel server chassis. Reference chassis designs may or may not require all of the connectors shown and different wiring material may be needed to meet specific platform requirements.
P3 Power Signal Connector • Connector housing: 5-pin Molex 50-57-9705 or equivalent • Contacts: Molex 16-02-0087 or equivalent Table 115: P3 Baseboard Signal Connector P4 Peripheral Connectors • Connector housing: AMP V0 P/N is 770827-1 or equivalent • Contact: Amp 61314-1 contact or equivalent Table 116: Peripheral Power Connectors P7 Hard Drive Back Plane Power Connector •...
enclosure). This grounding must be designed to ensure passing the maximum allowed Common Mode Noise levels. The power supply shall be provided with a reliable protective earth ground. All secondary circuits shall be connected to protective earth ground. Resistance of the ground returns to chassis shall not exceed 1.0 mΩ.
8.2.5 Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise. All outputs are measured with reference to the return remote sense signal (ReturnS). The 5V, 12V1, 12V2, +12V3, –12V and 5VSB outputs are measured at the power supply connectors referenced to ReturnS.
8.2.7 Capacitive Loading The power supply shall be stable and meet all requirements with the following capacitive loading ranges. Table 120: Capacitve Loading Conditions Output +3.3V +12V(1, 2, 3) -12V +5VSB 8.2.8 Closed Loop Stability The power supply shall be unconditionally stable under all line/load/transient load conditions including capacitive load ranges.
8.2.11 Soft Starting The power supply shall contain control circuit that provides monotonic soft start for its outputs without overstress of the AC line or any power supply components at any specified AC line or load conditions. There is no requirement for rise time on the 5V Standby but the turn on/off shall be monotonic.
Vout Vout Item Delay from AC being applied to 5VSB being within regulation. sb_on_delay Delay from AC being applied to all output voltages being ac_on_delay within regulation. Time all output voltages stay within regulation after loss of vout_holdup Delay from loss of AC to de-assertion of PWOK pwok_holdup Delay from PSON active to output voltages within regulation...
AC Input Vout AC_on_delay sb_on_delay PWOK 5VSB sb_vout PSON AC turn on/off cycle Figure 29. Turn On/Off Timing (Power Supply Signals) 8.2.14 Residual Voltage Immunity in Standby Mode The PS supply should be immune to any residual voltage placed on its outputs (Typically a leakage voltage through the system from standby output) up to 500mV.
Intel targets 10db margin to Class A Limits The Server Board SE7520JR2 has been has been tested and verified to comply with the following electromagnetic compatibility (EMC) regulations when installed a compatible Intel host system.
8.3.3 Certifications / Registrations / Declarations • UL Certification (US/Canada) • CE Declaration of Conformity (CENELEC Europe) • FCC/ICES-003 Class A Attestation (USA/Canada) • C-Tick Declaration of Conformity (Australia) • MED Declaration of Conformity (New Zealand) • BSMI Certification (Taiwan) •...
(1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, OR 97124-6497...
English translation of the notice above: Type of Equipment (Model Name): On License and Product Certification No.: On RRL certificate. Obtain certificate from local Intel representative Name of Certification Recipient: Intel Corporation Date of Manufacturer: Refer to date code on product Manufacturer/Nation: Intel Corporation/Refer to country of origin marked on product Revision 1.0...
Miscellaneous Board Information Updating the System Software To ensure your Server Board SE7520JR2 has the latest board fixes, it is highly recommended to load the latest system software. These include System BIOS, mBMC firmware, and FRUSDR Utility. It may also include Intel Management Module (IMM) BMC Firmware (if installed) and Hot Swap Controller (HSC) firmware if the baseboard is installed into an Intel server chassis with a backplane.
Failure to run the FRUSDR Update Utility may cause the platform management sub-system to report false errors causing your platform to operate erratically. Note: It is highly recommended that you update your Server Board SE7520JR2 with the latest system software, including the FRUSDR Update Utility. These can be downloaded from the following Intel web site: http://support.intel.com/support/motherboards/server/se7520jr2/...
BIOS image. If this option is not successful and your system continues to exhibit CMOS corruption errors, you can attempt option 2. Option 2) • Obtain BIOS Update Package From the following Intel Web Site: :http://support.intel.com/support/motherboards/server/se7520jr2/ • Turn off the system •...
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• Recovery from multiple floppy disks. Prepare 2 blank disks. The first disk(disk0) must be made bootable Copy amiboot.000 to disk0, and amiboot.001 to disk1. • Execute BIOS Recovery set Recovery Boot Jumper by moving jumper J1H2 row B from Pins 1-2 to Pins Insert the recovery media to the appropriate drive or USB interface.
Appendix A: Integration and Usage Tips The following Integration and Usage Tips are provided to assist with answering miscellaneous questions about the Server Board SE7520JR2 or as a guide to assist with troubleshooting common errors. • The use of DDR2 - 400 MHz or DDR - 266/333 MHz DIMMs is dependant on which board SKU is used.
Field replaceable unit Front side Bus 1024 MB. GPIO General purpose I/O Gunning Transistor Logic Hot-swap controller Hertz (1 cycle/second) Inter-integrated circuit bus Intel® architecture Input buffer I/O controller hub ICMB Intelligent Chassis Management Bus IERR Internal error Glossary Definition C78844-002 Revision 1.0...
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Term I/O and firmware bridge Intel Management Module INTR Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface Infrared In-target probe 1024 bytes. Keyboard controller style Local area network Liquid crystal display Light Emitting Diode Low pin count...
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Term SEEPROM Serial electrically erasable programmable read-only memory System Event Log Server Input/output Server management interrupt. SMI is the highest priority nonmaskable interrupt. Server management mode. Server management software SNMP Simple Network Management Protocol. To Be Determined TBSG Thermal Interface Material UART universal asynchronous receiver/transmitter User Datagram Protocol.