Memory Error Handling In Ras Mode - Intel SE7520JR2 Technical Manual

Error Reporting and Handling
does not alter the BSP and attempts to boot from the original BSP. Error messages are
displayed on the console, and errors are logged in the event log of a processor failure.
If the user replaces a processor that has been marked bad by the system, the system must be
informed about this change by running BIOS Setup and selecting that processor to be retested.
If a bad processor is removed from the system, the BMC automatically detects this condition
and clears the status flag for that processor during the next boot.
Three states are possible for each processor slot:
• Processor installed (status only, indicates processor has passed BIOS POST).
•
Processor failed. The processor may have failed FRB2, FRB3, or BIST, and it has been
disabled.
• Processor not installed (status only, indicates the processor slot has no processor in it).
Additional information on the FRB may be found in the Sahalee Baseboard Management
Controller EPS.
6.2 Memory Error Handling
The chipset will detect and correct single-bit errors and will detect all double-bit memory errors.
The chipset supports 4-bit single device data correction (SDDC) when in dual channel mode.
Both single-bit and double-bit memory errors are reported to baseboard management by the
BIOS, which handles SMI events generated by the MCH.
Memory Error Handling can be enabled or disabled in system BIOS Setup.
6.2.1

Memory Error Handling in RAS Mode

The MCH supports two memory RAS modes: Sparing and Mirroring. Enabling of Sparing or
Mirroring feature are mutually-exclusive. Use system BIOS Setup to configure memory RAS
mode.
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Intel® Server Board SE7520JR2
Revision 1.0