Exception Stack Frames - Motorola M68000 User Manual

Group Exception
0
Address Error
Bus Error
1
Interrupt
Privilege
2 TRAP, TRAPV,
Zero Divide

6.2.4 Exception Stack Frames

Exception processing saves the most volatile portion of the current processor context on
the top of the supervisor stack. This context is organized in a format called the exception
stack frame. Although this information varies with the particular processor and type of
exception, it always includes the status register and program counter of the processor
when the exception occurred.
The amount and type of information saved on the stack are determined by the processor
type and exception type. Exceptions are grouped by type according to priority of the
exception.
Of the group 0 exceptions, the reset exception does not stack any information. The
information stacked by a bus error or address error exception in the MC68000,
MC68HC000, MC68HC001, MC68EC000, or MC68008 is described in 6.3.9.1 Bus Error
and shown in Figure 6-7.
The MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008 group 1 and 2
exception stack frame is shown in Figure 6-5. Only the program counter and status
register are saved. The program counter points to the next instruction to be executed after
exception processing.
The MC68010 exception stack frame is shown in Figure 5-6. The number of words
actually stacked depends on the exception type. Group 0 exceptions (except reset) stack
29 words and group 1 and 2 exceptions stack four words. To support generic exception
handlers, the processor also places the vector offset in the exception stack frame. The
format code field allows the return from exception (RTE) instruction to identify what
information is on the stack so that it can be properly restored. Table 6-4 lists the MC68010
format codes. Although some formats are specific to a particular M68000 Family
processor, the format 0000 is always legal and indicates that just the first four words of the
frame are present.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
Table 6-3. Exception Grouping and Priority
Reset Exception Processing Begins within Two Clock Cycles
Trace Exception Processing Begins before the Next Instruction
Illegal
Exception Processing Is Started by Normal Instruction Execution
CHK
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