Cpu Space Cycle - Motorola M68000 User Manual

STATE 12 The write portion of the cycle starts in S12. The valid function codes on
FC2–FC0, the address bus lines, AS, and R/W remain unaltered.
STATE 13 During S13, no bus signals are altered.
STATE 14 On the rising edge of S14, the processor drives R/W low.
STATE 15 During S15, the data bus is driven out of the high-impedance state as the
data to be written are placed on the bus.
STATE 16 At the rising edge of S16, the processor asserts U D S or L D S . The
processor waits for DTACK or BERR or VPA, an M6800 peripheral signal.
When VPA is asserted during S16, the cycle becomes a peripheral cycle
(refer to Appendix B M6800 Peripheral Interface). If neither termination
signal is asserted before the falling edge at the close of S16, the processor
inserts wait states (full clock cycles) until either DTACK or BERR is asserted.
STATE 17 During S17, no bus signals are altered.
STATE 18 During S18, no bus signals are altered.
STATE 19 On the falling edge of the clock entering S19, the processor negates AS,
UDS, and LDS. As the clock rises at the end of S19, the processor
places the address and data buses in the high-impedance state, and drives
R/W high. The device negates DTACK or BERR at this time.

5.1.4 CPU Space Cycle

A CPU space cycle, indicated when the function codes are all high, is a special processor
cycle. Bits A16–A19 of the address bus identify eight types of CPU space cycles. Only the
interrupt acknowledge cycle, in which A16–A19 are high, applies to all the
microprocessors described in this manual. The MC68010 defines an additional type of
CPU space cycle, the breakpoint acknowledge cycle, in which A16–A19 are all low. Other
configurations of A16–A19 are reserved by Motorola to define other types of CPU cycles
used in other M68000 Family microprocessors. Figure 5-10 shows the encoding of CPU
space addresses.
FUNCTION
CODE
2
BREAKPOINT
1 1
ACKNOWLEDGE
(MC68010 only)
INTERRUPT
1 1
ACKNOWLEDGE
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
0 31 23
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 5-10. CPU Space Address Encoding
For More Information On This Product,
Go to: www.freescale.com
ADDRESS BUS
19 16
CPU SPACE
TYPE FIELD
0
3 1 0
LEVEL 1
5- 9