Shift/Rotate Instruction Execution Times - Motorola M68000 User Manual

CLR
NBCD
NEG
NEGX
NOT
Scc
TAS
TST
+Add effective address calculation time.

7.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES

Table 7-8 lists the timing data for the shift and rotate instructions. The total number of
clock periods, the number of read cycles, and the number of write cycles are shown in the
previously described format. The number of clock periods, the number of read cycles, and
the number of write cycles, respectively, must be added to those of the effective address
calculation where indicated by a plus sign (+).
Table 7-8. Shift/Rotate Instruction Execution Times
ASR, ASL
LSR, LSL
ROR, ROL
ROXR, ROXL
+Add effective address calculation time for word operands.
n is the shift count.
7-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
Table 7-7. Single Operand Instruction
Execution Times
Instruction Size
Byte
Word
Long
Byte
Byte
Word
Long
Byte
Word
Long
Byte
Word
Long
Byte, False
Byte, True
Byte
Byte
Word
Long
Instruction Size
Byte
Word
Long
Byte
Word
Long
Byte
Word
Long
Byte
Word
Long
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Register Memory
8(2/0) 12(2/1)+
8(2/0) 16(2/2)+
10(2/0) 24(2/4)+
10(2/0) 12(2/1)+
8(2/0) 12(2/1)+
8(2/0) 16(2/2)+
10(2/0) 24(2/4)+
8(2/0) 12(2/1)+
8(2/0) 16(2/2)+
10(2/0) 24(2/4)+
8(2/0) 12(2/1)+
8(2/0) 16(2/2)+
10(2/0) 24(2/4)+
8(2/0) 12(2/1)+
10(2/0) 12(2/1)+
8(2/0) 14(2/1)+
8(2/0) 8(2/0)+
8(2/0) 8(2/0)+
8(2/0) 8(2/0)+
Register Memory
10+2n (2/0) —
10+2n (2/0) 16(2/2)+
12+n2 (2/0) —
10+2n (2/0) —
10+2n (2/0) 16(2/2)+
12+n2 (2/0) —
10+2n (2/0) —
10+2n (2/0) 16(2/2)+
12+n2 (2/0) —
10+2n (2/0) —
10+2n (2/0) 16(2/2)+
12+n2 (2/0) —
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