Bus Arbitration - Motorola M68000 User Manual

The breakpoint acknowledge cycle is performed by the MC68010 to provide an indication
to hardware that a software breakpoint is being executed when the processor executes a
breakpoint (BKPT) instruction. The processor neither accepts nor sends data during this
cycle, which is otherwise similar to a read cycle. The cycle is terminated by either DTACK,
BERR, or as an M6800 peripheral cycle when V P A is asserted, and the processor
continues illegal instruction exception processing. Figure 5-12 illustrates the timing
diagram for the breakpoint acknowledge cycle.
S0 S2
CLK
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D15–D8
D7–D0
Figure 5-12. Breakpoint Acknowledge Cycle Timing Diagram

5.2 BUS ARBITRATION

Bus arbitration is a technique used by bus master devices to request, to be granted, and
to acknowledge bus mastership. Bus arbitration consists of the following:
1. Asserting a bus mastership request
2. Receiving a grant indicating that the bus is available at the end of the current cycle
3. Acknowledging that mastership has been assumed
There are two ways to arbitrate the bus, 3-wire and 2-wire bus arbitration. The MC68000,
MC68HC000, MC68EC000, MC68HC001, MC68008, and MC68010 can do 2-wire bus
arbitration. The MC68000, MC68HC000, MC68HC001, and MC68010 can do 3-wire bus
arbitration. Figures 5-13 and 5-15 show 3-wire bus arbitration and Figures 5-14 and 5-16
show 2-wire bus arbitration. Bus arbitration on all microprocessors, except the 48-pin
MC68008 and MC68EC000, BGACK must be pulled high for 2-wire bus arbitration.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
S4 S6 S0 S2
WORD READ BREAKPOINT
For More Information On This Product,
Go to: www.freescale.com
S4 S6 S0 S2
STACK PC LOW
CYCLE
S4 S6
5- 11