Motorola M68000 User Manual page 31

PROCESSOR
STATUS
MC6800
PERIPHERAL
CONTROL
SYSTEM
CONTROL
Figure 3-4. Input and Output Signals (MC68008, 48-Pin Version)
PROCESSOR
STATUS
MC6800
PERIPHERAL
CONTROL
SYSTEM
CONTROL
Figure 3-5. Input and Output Signals (MC68008, 52-Pin Version)
3.1 ADDRESS BUS (A23–A1)
This 23-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data.
This bus provides the address for bus operation during all cycles except interrupt
acknowledge cycles and breakpoint cycles. During interrupt acknowledge cycles, address
lines A1, A2, and A3 provide the level number of the interrupt being acknowledged, and
address lines A23–A4 are driven to logic high.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
V CC (2)
GND(2)
CLK
FC0
FC1
FC2
MC6808
E
VPA
BERR
RESET
HALT
V CC
GND(2)
CLK
FC0
FC1
FC2
MC68008
E
VPA
BERR
RESET
HALT
For More Information On This Product,
Go to: www.freescale.com
ADDRESS
BUS A19–A0
DATA BUS D7–D0
AS
ASYNCHRONOUS
R/W
BUS
DS
CONTROL
DTACK
BUS
BR
ARBITRATION
BG
CONTROL
IPL2/IPL0
INTERRUPT
IPL1
CONTROL
ADDRESS
BUS A21–A0
DATA BUS D7–D0
AS
ASYNCHRONOUS
R/W
BUS
DS
CONTROL
DTACK
BR
BUS
BG ARBITRATION
CONTROL
BGACK
IPL0
INTERRUPT
IPL1
CONTROL
IPL2
3- 3