Motorola M68000 User Manual page 25

Table 2-2. Instruction Set Summary (Sheet 1 of 4)
Opcode
ABCD Source 10 + Destination 10 + X
ADD Source + Destination
ADDA Source + Destination
ADDI Immediate Data + Destination
ADDQ Immediate Data + Destination
ADDX Source + Destination + X
AND Source Destination
ANDI Immediate Data
ANDI to CCR Source CCR
ANDI to SR If supervisor state
then Source
else TRAP
ASL, ASR Destination Shifted by <count>
Bcc If (condition true) then PC + d
BCHG ~ (<number> of Destination)
~ (<number> of Destination)
BCLR ~ (<bit number> of Destination)
0 <bit number> of Destination
BKPT Run breakpoint acknowledge cycle;
TRAP as illegal instruction
BRA PC + d PC
BSET ~ (<bit number> of Destination)
1 <bit number> of Destination
BSR SP – 4 SP; PC
BTST – (<bit number> of Destination)
CHK If Dn < 0 or Dn > Source then TRAP
CLR 0 Destination
CMP Destination—Source
CMPA Destination—Source
CMPI Destination —Immediate Data
CMPM Destination—Source
DBcc If condition false then (Dn – 1
If Dn –1 then PC + d
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER'S MANUAL
Freescale Semiconductor, Inc.
Operation
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination Destination
CCR
SR SR
Destination
PC
Z;
<bit number> of Destination
Z;
Z;
(SP); PC + d PC
Z;
cc
cc
Dn;
PC)
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S y n t a x
ABCD Dy,Dx
ABCD –(Ay), –(Ax)
ADD <ea>,Dn
ADD Dn,<ea>
ADDA <ea>,An
ADDI # <data>,<ea>
ADDQ # <data>,<ea>
ADDX Dy, Dx
ADDX –(Ay), –(Ax)
AND <ea>,Dn
AND Dn,<ea>
ANDI # <data>, <ea>
ANDI # <data>, CCR
ANDI # <data>, SR
ASd Dx,Dy
ASd # <data>,Dy
ASd <ea>
Bcc <label>
BCHG Dn,<ea>
BCHG # <data>,<ea>
BCLR Dn,<ea>
BCLR # <data>,<ea>
BKPT # <data>
BRA <label>
BSET Dn,<ea>
BSET # <data>,<ea>
BSR <label>
BTST Dn,<ea>
BTST # <data>,<ea>
CHK <ea>,Dn
CLR <ea>
CMP <ea>,Dn
CMPA <ea>,An
CMPI # <data>,<ea>
CMPM (Ay)+, (Ax)+
DBcc Dn,<label>
2-11