Motorola M68000 User Manual page 83

On the rising edge of the clock, at the end of S7 (which may be the start of
S0 for the next bus cycle), the processor places the address bus in the
high-impedance state. During a write cycle, the processor also places the
data bus in the high-impedance state and drives R/W high. External logic
circuitry should respond to the negation of the AS and UDS, LDS, and/or DS
by negating DTACK and/or BERR. Parameter #28 is the hold time for
DTACK, and parameter #30 is the hold time for BERR.
Figure 5-35 shows a synchronous read cycle and the important timing parameters that
apply. The timing for a synchronous read cycle, including relevant timing parameters, is
shown in Figure 5-36.
CLOCK
6
ADDR
AS
UDS/LDS
R/W
DTACK
DATA
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
S0 S1 S2 S3
9
18
Figure 5-35. Synchronous Read Cycle
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S4 S5 S6
47
27
S7 S0
5- 37