Motorola M68000 User Manual page 71

S0
CLK
FC2–FC0
A23–A1
AS
UDS/LDS
R/W
DTACK
D15–D0
BERR
HALT
Figure 5-26. Delayed Bus Error Timing Diagram (MC68010)
After the aborted bus cycle is terminated and BERR is negated, the processor enters
exception processing for the bus error exception. During the exception processing
sequence, the following information is placed on the supervisor stack:
1. Status register
2. Program counter (two words, which may be up to five words past the instruction
being executed)
3. Error information
The first two items are identical to the information stacked by any other exception. The
error information differs for the MC68010. The MC68000, MC68HC000, MC68HC001,
MC68EC000, and MC68008 stack bus error information to help determine and to correct
the error. The MC68010 stacks the frame format and the vector offset followed by 22
words of internal register information. The return from exception (RTE) instruction restores
the internal register information so that the MC68010 can continue execution of the
instruction after the error handler routine completes.
After the processor has placed the required information on the stack, the bus error
exception vector is read from vector table entry 2 (offset $08) and placed in the program
counter. The processor resumes execution at the address in the vector, which is the first
instruction in the bus error handler routine.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
S2 S4 S6
BUS ERROR
READ CYCLE
DETECTION
For More Information On This Product,
Go to: www.freescale.com
INITIATE BUS
ERROR STACKING
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