Motorola M68000 User Manual page 64

BUS THREE-STATED
BG ASSERTED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED
CLK
S0 S1 S2 S3 S4 S5 S6 S7
BR
BG
BGACK
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D15–D0
PROCESSOR
Figure 5-19. 3-Wire Bus Arbitration Timing Diagram—Processor Active
5-18 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE
BGACK NEGATED INTERNAL
BGACK SAMPLED
BGACK NEGATED
ALTERNATE BUS MASTER
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S0 S1 S2 S3 S4 S5 S6 S7 S0 S1
PROCESSOR
MOTOROLA