Motorola M68000 User Manual page 58

PROCESSOR
GRANT BUS ARBITRATION
1) ASSERT BUS GRANT (BG)
TERMINATE ARBITRATION
1) NEGATE BG (AND WAIT FOR BGACK
TO BE NEGATED)
REARBITRATE OR RESUME
PROCESSOR OPERATION
Figure 5-13. 3-Wire Bus Arbitration Cycle Flowchart
(Not Applicable to 48-Pin MC68008 or MC68EC000)
5-12 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
REQUESTING DEVICE
REQUEST THE BUS
1) ASSERT BUS REQUEST (BR)
ACKNOWLEDGE BUS MASTERSHIP
1) EXTERNAL ARBITRATION DETER-
MINES NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE
3) NEXT BUS MASTER ASSERTS BUS
GRANT ACKNOWLEDGE (BGACK)
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR
OPERATE AS BUS MASTER
1) PERFORM DATA TRANSFERS (READ
AND WRITE CYCLES) ACCORDING
TO THE SAME RULES THE PRO-
CESSOR USES
RELEASE BUS MASTERSHIP
1) NEGATE BGACK
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