Table 8-12. Miscellaneous Instruction Execution Times
Instruction
ANDI to CCR
ANDI to SR
CHK (No Trap)
EORI to CCR
EORI to SR
ORI to CCR
ORI to SR
MOVE from SR
MOVE to CCR
MOVE to SR
EXG
EXT
LINK
MOVE from USP
MOVE to USP
NOP
RESET
RTE
RTR
RTS
STOP
SWAP
TRAPV
UNLK
+Add effective address calculation time.
Table 8-13. Move Peripheral Instruction Execution Times
Instruction
MOVEP
8.12 EXCEPTION PROCESSING EXECUTION TIMES
Table 8-14 lists the timing data for exception processing. The numbers of clock periods
include the times for all stacking, the vector fetch, and the fetch of the first instruction of
8-10
MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL
Freescale Semiconductor, Inc.
Size
Byte
Word
—
Byte
Word
Byte
Word
—
—
—
—
Word
Long
—
—
—
—
—
—
—
—
—
—
—
—
Size
Register
Word
16(2/2)
Long
24(2/4)
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Memory
20(3/0)
20(3/0)
10(1/0)+
20(3/0)
20(3/0)
20(3/0)
20(3/0)
6(1/0)
8(1/1)+
12(1/0)
12(1/0)+
12(2/0)
12(2/0)+
6(1/0)
4(1/0)
4(1/0)
16(2/2)
4(1/0)
4(1/0)
4(1/0)
132(1/0)
20(5/0)
20(2/0)
16(4/0)
4(0/0)
4(1/0)
4(1/0)
12(3/0)
Memory
Memory
16(4/0)
24(6/0)
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