Interrupts - Gateway ALR 9200 Maintaining And Troubleshooting

Note:
If you disable either IDE
controller to free the
interrupt for that controller,
you must physically unplug
the IDE cable from the
system board. Simply
disabling the drive by
configuring the SSU option
does not make the interrupt
available.
182 Maintaining and Troubleshooting the Gateway ALR 9200 Server

Interrupts

Table 39 suggests a logical interrupt mapping of interrupt sources; it
reflects a typical configuration, but you can change these interrupts. Use
the information to determine how to program each interrupt. The actual
interrupt map is defined using configuration registers in the PIIX4E and the
I/O controller. I/O Redirection Registers in the I/O APIC are provided for
each interrupt signal; the signals define hardware interrupt signal
characteristics for APIC messages sent to local APIC(s).
Interrupt I/O APIC
Level
INTR INT0
NMI N/A
IRQ1 INT1
Cascade INT2
IRQ3 INT3
IRQ4 INT4
IRQ5 INT5
IRQ6 INT6
IRQ7 INT7
IRQ8_L INT8
IRQ9 INT9
IRQ10 INT10
IRQ11 INT11
IRQ12 INT12
IRQ13 INT13
IRQ14 INT14
IRQ15 INT15
SMI_L
Table 39: Interrupts
Description
Processor interrupt
NMI from PIC to processor
Keyboard interrupt
Interrupt signal from second 8259 in PIIX4E
Serial port A or B interrupt from SIO device (you can configure
either)
Serial port A or B interrupt from SIO device (you can configure
either)
Parallel port II
Diskette port
Parallel port
RTC interrupt
Signal control interrupt (SCI) used by ACPI-compliant
operating system
Mouse interrupt
Co-processor interrupt
Compatibility IDE interrupt from primary channel IDE devices
0 and 1
System management interrupt—general purpose indicator
sourced by the PIIX4E and BMC through the PID to the
processors