Advanced Chipset Control Submenu - Gateway ALR 9200 Maintaining And Troubleshooting

Advanced Chipset Control Submenu

The advanced chipset control submenu provides several fields that allow
you to control various advanced features of the chipset. Table 17 lists the
fields and the options for each.
Table 17: Advanced Chipset Control Submenu
Field Options
Address Bit Disabled
Permuting Enabled
Base RAM Step 1 MB
1 KB
Every location
Extended RAM 1 MB
Step 1 KB
Every location
L2 Cache Enabled
Disabled
ISA Expansion Enabled
Aliasing Disabled
Memory Scrubbing Disabled
Enabled
Restreaming Buffer Enabled
Disabled
Read Prefetch for N/A
PXB0A
Read Prefetch for N/A
PXB0B
Description
To be enabled, there must be a power of 2 number
of rows (2, 4, 8, or 16), all rows must be the same
size, and all populated rows must be adjacent and
start at row 0. Two-way or four-way permuting is
set automatically based on memory configuration.
Tests base memory once per MB, once per KB, or
at every location.
Tests extended memory once per MB, once per
KB, or at every location.
When enabled, the secondary cache is sized and
enabled. For Core Clock Frequency-to-System
Bus ratios equal to two, BIOS automatically
disables the L2 cache.
When enabled, every I/O access with an address in
the range x100-x3FFh, x500-x7FFh, x900-xBFF,
and xD00-xFFFh is internally aliased to the range
0100-03FFh before any other address range
checking is performed.
When enabled, BIOS automatically detects and
corrects single bit errors (SBEs).
When enabled, the data returned and buffered for
a Delayed Inbound Read can be reaccessed
following a disconnect.
Informational field only. Configures the number of
Dwords that are prefetched on Memory Read
Multiple commands.
Informational field only. Configures the number of
Dwords that are prefetched on Memory Read
Multiple commands.
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