I/O Functionality; Table 5. Cpu Bus Connector J8 - ZiLOG eZ80F92 User Manual

Signal
A[0:7]
A[8:15]
A[16:23]
RD
RESET
BUSACK
NMI
D[0:7]
CS[0:3]
MREQ
WR
INSTRD
BUSREQ
PHI
Note: *All of the signals except BUSACK and INSTRD are driven by low-voltage
CMOS technology (LVC) drivers.

I/O Functionality

The eZ80190 microprocessor features General-Purpose I/O functionality
at Port A. The eZ80F92 device does not incorporate this Port A feature.
The eZ80
featuring GPIO for devices without Port A, an LED matrix, a modem
reset, and two user triggers.
UM013904-0203

Table 5. CPU Bus Connector J8*

Pin # Function
3–10 Address Bus, Low Byte
13–20 Address Bus, High Byte
23–30 Address Bus, Upper Byte
33 Read Signal
35 Push Button Reset
37 CPU Bus Acknowledge Signal
39 Nonmaskable Interrupt
43–50 Data Bus
53–56 Chip Selects
57 Memory Request
34 WRITE Signal
36 Instruction Fetch
38 CPU Bus Request signal
40 Clock output of the CPU
®
Development Platform provides additional I/O functionality,
PRELIMINARY
eZ80F92 Development Kit
User Manual
Direction
Output
Output
Output
Output
Output
Output
Input
Bidirectional
Output
Output
Output
Output
Operational Description
23