I/O Functionality; Table 5. Cpu Bus Connector J8 - ZiLOG eZ80L92 User Manual

Signal
A[0:7]
A[8:15]
A[16:23]
RD
RESET
BUSACK
NMI
D[0:7]
CS[0:3]
MEMRQ
WR
INSTRD
BUSREQ
PHY
Note: *All of the signals except BUSACK and INSTRD are driven by low-
voltage CMOS technology (LVC) drivers.

I/O Functionality

The eZ80
ing general-purpose port, an LED matrix, a modem reset, and two user trig-
gers. These functions are memory-mapped with an address decoder based
on the Generic Array Logic GAL22lV10D (U15) device manufactured by
Lattice Semiconductor, and a bidirectional latch (U16). Additionally, U15 is
used to decode addresses for access to the 7x5 LED matrix.
UM012906-0103

Table 5. CPU Bus Connector J8*

Pin # Function
3–10 Address Bus, Low Byte
13–20 Address Bus, High Byte
23–30 Address Bus, Upper Byte
33 READ Signal
35 Push Button Reset
37 CPU Bus Acknowledge Signal
39 Nonmaskable Interrupt
43–50 Data Bus
53–56 Chip Selects
57 Memory Request
34 WRITE Signal
36 Instruction Fetch
38 CPU Bus Request signal
40 Clock output of the CPU
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Direction
Output
Output
Output
Output
Output
Output
Input
Bidirectional
Output
Output
Output
Output
Operational Description
23