4-6.4.1 Northbridge Configuration - SOLTEK SL-B5A-FG Manual

SL-B5A-FG / B5A-FGR

4-6.4.1 NorthBridge Configuration

Choose "NorthBridge Configuration" in "Advanced Chipset Features"
and press <Enter>. The following sub-screen will appear for
configuration:
North Bridge Chipset Configuration
DRAM Frequency
Configure DRAM Timing by SPD
Memory Hole
Boots Graphic Adapter Priority
Internal Graphics Mode Select
Graphics Aperture Size
PEG Port Configuration
PEG Port
PEG Port VC1/Map
PEG Force x1
Video Function Configuration
DRAM Frequency
Configure SDRAM Timing by SPD
SPD (Serial presence detect) is a device in memory module for storing the module information
such as DRAM timing and chip parameters. If this option is enabled, BIOS will access SPD
automatically to configure module timing. If disabled, the following items will appear for user's
configuration:
DRAM CAS# Latency
With SDRAM Timing by SPD disabled, you can select the SDRAM CAS# (Column Address
Strode)latency manually.
Choices: 2 Clocks; 2.5 Clocks; 3 Clocks
DRAM RAS# to CAS# Delay
With SDRAM Timing by SPD disabled, you can select the SDRAM RAS# to CAS# delay
cycle manually.
Choices: 2 DRAM Clocks; 3 DRAM Clocks; 4 DRAM Clocks; 5 DRAM Clocks
DRAM RAS# Precharge
With SDRAM Timing by SPD disabled, you can select the SDRAM RAS# (Row Address
Strode)Precharge cycle manually.
Choices: 2 Clocks; 3 Clocks; 4 Clocks; 5 Clocks
DRAM RAS# Activate to Prec
Allows you to set the DRAM RAS Activate to Precharge cycle.
Choices: 4 Clocks ~15 Clocks with 1 clock stepping
North Bridge Configuration
Auto
Enabled
Disabled
PEG/PCI
Enabled, 8MB
256MB
Enabled
Enabled/TC7
Disabled
Press Enter
Allows you to set the current SDRAM frequency.
Choices: Auto; 333MHz; 400MHz
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Chapter 4 BIOS Setup
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