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These tabs are used to define the entire PF5030 OTP configuration.
When the OTP configuration is defined, TBB/OTP scripts can be generated using the Export menu. Generate a
TBB file for emulation and an OTP file for OTP programming.
It is possible to save a configuration to use or modify it later. To export the OTP configuration, click "Save
Config". To import a configuration initially saved from the OTP tool or the Mirrors tab, click the Import button.
6.3.1 System configuration tab
The system configuration tab has several sections, divided into two groups. The first group is related to OTP
configuration itself:
• System Configuration: I
assignment
• Clock and Synchronization: Clock modulation, XFAILB synchronization
• VMON OV Deep Fail-safe Reaction: configures device reaction when OV event is detected.
• Power Sequence Configuration: This box is used to define the power sequence of the device and device
reaction when TSD happens. If the configuration is modified, the power-up sequence graph is updated
automatically.
Figure 23
shows an OTP configuration example.
Figure 23. OTP System Configuration Tab, part 1 of 2: OTP configuration
The second group is related to VMON board connection and startup sequence diagram:
• Voltage monitoring recap for power-up sequence diagram drawing: This box is NOT related to the OTP
configuration. It allows the definition of an assignment between the VMONx and the regulators to plot the
power-up sequence graph. It does not configure any registers. It is only used as information. It is saved as
comment on the configuration script.
• Power-up sequence diagram: This diagram reflects the power-up sequence of the PF5030 depending on the
OTP configuration. To plot the associated configuration, it uses the "Voltage Monitoring Recap". The power-
up sequence timing may not be 100 % accurate. If shown, the RSTB, the FOUT, and the XFAILB voltages are
different from 3.3 V to differentiate between the different curves.
Figure 24
shows a voltage monitoring recap connection and the resulting power-up sequence diagram.
UM11854
User manual
2
C addresses, VIN threshold, program ID, fault retry management, regulator
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2023
KITPF5030SKTEVM programming board
UM11854
© 2023 NXP B.V. All rights reserved.
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