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NXP Semiconductors
7 Using an evaluation board
Before starting the process, consult the development board scheme and user manual to configure the required
use case.
Learn about OTP before operating with the device. The device has a high level of flexibility due to the parameter
configuration available in the OTP. It impacts the functionality of the device. It is key to understand how OTP
parameters can be programmed, the interaction with mirror registers, and the PF5030 device.
The OTP-related operations can only be performed in test mode (emulation) and OTP mode (programming,
test mode is enabled automatically). When using emulation, the device loses the configuration when the power
supply is switched off, when the device enters deep fail-safe (DEEP-FS) state, or when it goes standby.
7.1 OTP and mirrors registers
The device incorporates two OTP blocks. One is for the main section, the other for the fail-safe section. During
configuration, each of them uses dedicated sectors.
Each block is divided in two sectors, S1 and S1bis respectively, so the device can be fused two times. The OTP
configuration scheme is shown in
Figure 45. OTP block diagram
At device starts-up, the content of the valid (last programmed) sector is loaded into mirror registers. The mirror
register content is accessible from the NXP GUI, using specific I
mirror configuration, which facilitates access. The mirror register content handling is called "OTP emulation".
To burn the OTP configuration, the mirror register content must be loaded with the desired content. Then a
command must be sent to burn the mirror content to the next available OTP sector. The first sector to be burned
is S1, the second S1bis. The NXP GUI automatically manages the next sector to be burned. It is not possible
to revert to the previous sector. When the user reaches the sector S1bis, there is no other possibility for burn.
However, the emulation is still available.
7.2 Device modes
There are several modes that describe device operation.
There are three modes to run the device:
• User mode: Only user-related registers can be accessed and handled.
• OTP mode: OTP fuse content loaded to mirror registers. OTP programming / emulation (mirror registers
handling) possible.
• Test mode: OTP programming and mirror registers handling (emulation) granted.
There are two modes to run the device related to the fail-safe state machine:
• Normal mode: Watchdog windowing and initialization (INIT_FS state) timeout depend on OTP configuration.
• Debug mode: Watchdog windowing disabled, no initialization timeout, fail-safe safety reactions disabled.
Debug and OTP modes are enabled by applying voltage on DBG pin during startup and/or restart.
UM11854
User manual
Figure 45
(same implementation for main and fail-safe).
Device
Mirror
configuration
register
GUI/
S1 - Config
Device interface
Primary CONFIG
Images CONFIG
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2023
KITPF5030SKTEVM programming board
OTP Fuse
configuration
S1 - Config
S1bis - Config
aaa-044291
2
C commands. The NXP GUI manages the
UM11854
© 2023 NXP B.V. All rights reserved.
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