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UM11854
NXP Semiconductors
KITPF5030SKTEVM programming board
commands to the main state and the fail-safe state machine to exit OTP mode and initiate device start-up. The
addresses are automatically updated to keep device communication.
Test mode can be enabled and disabled by clicking the Test Mode button when DBG pin voltage is 7.95 V (EVB
OTP mode LED on). When the button is green, Test mode is activated. The button state can also be refreshed
by clicking the arrow loop buttons.
Figure 27. GUI and device in test mode
The current device mode (user / test) is shown on the device status bar.
Test mode can be entered when device is not in OTP mode.
When in OTP mode, the device is necessarily in Debug mode.
6.5 OTP mode and device programming
Device enters OTP mode when the DBG pin voltage is set to 7.95 V before start-up. The OTP mode consists
2
of a device state machine stop at Main/FS OTP MODE states. When in Main/FS OTP mode states, the I
C
addresses are 0x20 for main and 0x21 for fail-safe. The Main/FS OTP mode states are left when one of these
conditions is met:
• Imposing DBG pin voltage inferior to 5.5 V
2
• Sending Main/FS OTP mode exit command through I
C
• Clicking NXP GUI button "Exit OTP Mode"
The NXP GUI is able to identify these addresses automatically from the device.
Then, the device addresses are set based on the mirror registers values. User can only change these
addresses in the mirror register in Test mode.
6.5.1 Device programming
The Device Programming tab shown in
Figure 28
allows OTP device programming using a file initially
generated by the OTP tool. This tab is only available when Test mode is active.
UM11854
All information provided in this document is subject to legal disclaimers.
© 2023 NXP B.V. All rights reserved.
User manual
Rev. 1 — 9 March 2023
33 / 56
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