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NXP Semiconductors
4.3.3 VDDIO
The VDDIO pin is powered through VDDIO net and is used to supply internal buffers and I
The selection of VDDIO is made using J14 connector as shown in
provided to feed VDDIO through the VDDIO_SEL net.
Figure 4. VDDIO selection
2
The I
C is compatible with 1.8 V, 3.3 V, and 5.0 V, therefore VDDIO_SEL voltage is configurable between 1.8 V,
3.3 V, or 5.0 V using J18 and J19 connectors (3.3 V by default) shown in
R105
P5V_KL25Z
0 Ω
R106
VIN_5V
0 Ω
DNP
JUMPER (DEFAULT) = 1-2
SILK = J18 VDDIO_SEL: 1-2: J19/2-3: 5 V
Figure 5. VDDIO_SEL supply voltage selection
UM11854
User manual
VDDIO
VDDIO
VDDIO
C50
PWRG
1.0 µF
NCV8537MNADJR2G
GND
J18
1
2
3
All information provided in this document is subject to legal disclaimers.
Figure
J14
1
2
LDO1
3
4
LDO2
5
6
VDDIO_EXT
7
8
VDDIO_SEL
9
10
VIN_3V3
HDR 2X5
JUMPER (DEFAULT) = 7-8
C67
10 nF
DNP
U11
6
7
SD
ADJ
8
VIN1
VOUT1
9
1
VIN2
VOUT2
10
2
5
4
11
GND
Rev. 1 — 9 March 2023
KITPF5030SKTEVM programming board
4. By default, an external LDO is
aaa-048952
Figure
5.
GND
GND
R88
115 kΩ
SILK = J19 VDDIO_SEL:
1-2: 1.8 V/2-3: 3.3 V
J19
JUMPER (DEFAULT) = 3-2
3
2
1
R80
R109
191 kΩ
71.5 kΩ
3.3 V
1.8 V
UM11854
2
C communication.
VDDIO_SEL
C51
2.2 µF
GND
aaa-048953
© 2023 NXP B.V. All rights reserved.
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