Schematic, Board Layout, And Bill Of Materials; Vmon Board Configuration - NXP Semiconductors KITPF5030SKTEVM User Manual

Programming board
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4.3 Schematic, board layout, and bill of materials

The schematic, board layout, and bill of materials for the KITPF5030SKTEVM board are available at
www.nxp.com/KITPF5030SKTEVM.

4.3.1 VMON board configuration

The VMON configuration is highly dependent on the use case. This kit is delivered with a default configuration.
The user can assign VMON_EXT differently to address the use case using J4 and J7 connectors shown in
Figure
1. J7 is used to select the VMON_EXT (VMON0) external resistor divider to monitor 3.3 V or 5.0 V. J4
is used to connect the VMON_EXT external resistor divider input VMON_EXT_INPUT to an external voltage,
VIN_3V3, or VIN_5V. By default, VMON_EXT is monitoring VIN_3V3.
VMON_EXT resistor bridges
VMON_EXT_INPUT
R27
37.4 kΩ
3.3 V to 0.8 V
J7
resistor bridge
HDR_1X3
Figure 1. VMON_EXT assignment (VIN_3V3 default)
By default, BUCK2_FB (VMON2) is connected to BUCK2 though R162. However, When BUCK2 is disabled or
used in multiphase with BUCK1, BUCK2_FB can be connected to an external voltage. R162 must be removed
in this case and the internal DAC must be configured to the voltage monitoring target.
By default, LDO1_MON (VMON4) and LDO2_MON (VMON5) pins are tied to LDO1 and LDO2, respectively.
LDO1_MON and LDO2_MON can be used to monitor an external voltage using test points TP25 (LDO1_MON)
and TP26 (LDO2_MON), then R154 and/or R156 must be removed.
the schematic. The internal resistors dividers can be configured to select the voltage monitoring target.
Figure 2. LDO1_MON and LDO2_MON input configuration
UM11854
User manual
R28
63.4 kΩ
5 V to 0.8 V
resistor bridge
1
2
3
VMON_EXT
R29
12 kΩ
GND
U1
LDO1_OUT
3
LDO1_MON
2
LDO2_OUT
37
LDO2_MON
38
All information provided in this document is subject to legal disclaimers.
DBG
PWRON
AMUX_OUT
R153
LDO1
0 Ω
R154
0 Ω
R155
LDO2
0 Ω
R156
0 Ω
Rev. 1 — 9 March 2023
KITPF5030SKTEVM programming board
PF5030
Signals
J4
1
2
VDDIO_EXT
3
4
5
6
7
8
9
10
11
12
VMON_EXT_INPUT
13
14
15
16
GND
Figure 2
shows the corresponding part of
LDO1_MON
TP25
LDO2_MON
TP26
aaa-048946
UM11854
http://
VDDIO
I2C_SCL
I2C_SDA
VIN_3V3
VIN_5V
aaa-048954
© 2023 NXP B.V. All rights reserved.
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