Intel altera Agilex 7 FPGA M-Series Instruction Manual
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Intel altera Agilex 7 FPGA M-Series Instruction Manual

Intel altera Agilex 7 FPGA M-Series Instruction Manual

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™
Agilex
7 Clocking and PLL User
Guide
M-Series
®
Updated for Quartus
Prime Design Suite: 24.1
769001
Online Version
Send Feedback
2024.04.01

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Summary of Contents for Intel altera Agilex 7 FPGA M-Series

  • Page 1 ™ Agilex 7 Clocking and PLL User Guide M-Series ® Updated for Quartus Prime Design Suite: 24.1 769001 Online Version Send Feedback 2024.04.01...

  • Page 2: Table Of Contents

    4.1. Release Information for Clock Control Intel FPGA IP..........32 4.2. Clock Control Intel FPGA IP Core Parameters............32 4.3. Clock Control Intel FPGA IP Core Ports and Signals........... 33 5. IOPLL Intel FPGA IP Core..................... 35 5.1. Release Information for IOPLL Intel FPGA IP............35 5.2.
  • Page 3 Contents 7. Document Revision History for the Agilex 7 Clocking and PLL User Guide: M-Series..41 Agilex 7 Clocking and PLL User Guide: M-Series Send Feedback...

  • Page 4: Agilex ™ 7 Fpga M-Series Clocking And Pll Overview

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 5: M-Series Clocking And Pll Architecture And Features

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
  • Page 6 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 pairs, where only one wire in each pair can be used at one time. At each corner, there is a set of programmable clock switch multiplexers that can route between these clock wires.

  • Page 7: Clock Resources

    2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 Figure 4. Examples of Clock Networks Sizes Using M-Series Device Programmable Clock Routing Total Clock Tree Span Balanced Clock Tree Route to Center of Clock Tree Clock Source (Pin or PLL Output) 2.1.2.

  • Page 8: Clock Control Features

    2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 Related Information Agilex 7 Device Family Pin Connection Guidelines: M-Series 2.1.3. Clock Control Features The following figure shows a high-level description of the M-Series clock control features—clock gating and clock divider. The clock from the I/O PLL output can be gated dynamically.
  • Page 9 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 Intel recommends using the clock gate with a negative latch to provide glitch free gating on the output clock signal ( ). The clock gate captures the enable signal...

  • Page 10: Plls Architecture And Features

    1 to 110 1 to 110 continued... I/O PLL Type is determined by the Intel Quartus Prime software automatically, based on the assigned location of the I/O PLL in Assignment Editor. Agilex 7 Clocking and PLL User Guide: M-Series Send Feedback...
  • Page 11 (10) Spread-spectrum input clock tracking I/O PLL Type is determined by the Intel Quartus Prime software automatically, based on the assigned location of the I/O PLL in Assignment Editor. For dedicated external clock outputs, you must enable access to external clock output port ®...

  • Page 12: Pll Usage

    2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 Table 3. Spread-Spectrum Input Clocking Supported Profile Spread-Spectrum Clocking Parameter Setting Modulation frequency 200 kHz Center or down spread Down spread Frequency deviation ±1% Modulation profile Triangle 2.2.2. PLL Usage I/O bank I/O PLLs are optimized for use with memory interfaces and LVDS SERDES.
  • Page 13 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 Figure 9. Fabric-feeding I/O PLL Location In UIBSS Fabric-Feeding Fabric-Feeding UIB IO I/O PLL I/O PLL UIB PHY HBMC UIB PLL Within an I/O bank, there is a top index sub-bank and a bottom index sub-bank placed near the edge of the die.

  • Page 14: Pll Architecture

    2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 2.2.4. PLL Architecture Figure 10. I/O Bank I/O PLL High-Level Block Diagram for M-Series Devices To DPA Block The CLKIN can come from core or dedicated clock inputs Lock locked ÷C1 Cascade Output...

  • Page 15: Pll Feedback Modes

    I/O PLL to emulate the insertion delay of the compensated counter output clock network. Intel recommends the non-dedicated feedback mechanism because it uses the clock resources most efficiently. Agilex 7 Clocking and PLL User Guide: M-Series Send Feedback...
  • Page 16 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 2.2.6.1. Direct Compensation Mode In direct mode, the PLL does not compensate for any clock network delays. This mode provides better jitter performance compared to other compensation modes because the clock feedback into the phase frequency detector (PFD) passes through less circuitry.
  • Page 17 Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard. Only one output clock can be compensated in source synchronous compensation mode. Intel recommends source synchronous mode for source synchronous data transfers. Figure 13. Example of Phase Relationship Between Clock and Data in Source...
  • Page 18 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 2.2.6.4. Normal Compensation Mode An internal clock in normal compensation mode is phase-aligned to the input clock pin. The external clock output pin has a phase delay relative to the clock input pin if connected in this mode.
  • Page 19 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 Figure 15. Example of Phase Relationship Between the PLL Clocks in ZDB Mode Phase Aligned PLL Reference Clock at the Input Pin The internal PLL clock PLL Clock at the output can lead or lag Register Clock Port the external PLL clock...

  • Page 20: Clock Multiplication And Division

    2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 Figure 16. Example of Phase Relationship Between the PLL Clocks in EFB Mode Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port The PLL clock outputs can lead or lag the fbin clock input.

  • Page 21: Programmable Phase Shift

    2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 software sets the VCO frequency to 1.1 GHz (the least common multiple of 55 MHz and 100 MHz within the VCO operating frequency range). Then the post-scale counters, , scale down the VCO frequency for each output port. Integer Mode The I/O PLL can only operate in integer mode.

  • Page 22: Pll Input Clock Switchover

    2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 • Cascading via dedicated cascade path—upstream I/O PLL and downstream I/O PLL must be in the same I/O column and are placed adjacently. • Cascading via core clock fabric—no restriction on locations of upstream and downstream I/O PLL.
  • Page 23 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 M-Series I/O PLLs support the following clock switchover modes: • Automatic switchover—the clock sense circuit monitors the current reference clock. If the current reference clock stops toggling, the reference clock automatically switches to clock.
  • Page 24 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 signal indicates which of the two clock inputs ( activeclock inclk0 inclk1 is being selected as the reference clock to the I/O PLL. When the frequency difference between the two clock inputs is more than 20%, the signal is the only activeclock valid status signal.
  • Page 25 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 Figure 20. Automatic Switchover After Loss of Clock Detection This figure shows an example waveform of the switchover feature in automatic switchover mode. In this example, the signal is held low. After the signal is held low for approximately two clock cycles, inclk0 inclk0...
  • Page 26 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 Figure 21. Clock Switchover Using the (Manual) Control extswitch This figure shows a clock switchover waveform controlled by the signal. In this case, both clock extswitch sources are functional and is selected as the reference clock.

  • Page 27: Pll Reconfiguration And Dynamic Phase Shift

    You can delay the clock switchover action by specifying the switchover delay in the Intel FPGA IP cores for the I/O PLL. When you specify the switchover delay, the signal must be held low for at least three cycles for the...
  • Page 28 2. M-Series Clocking and PLL Architecture and Features 769001 | 2024.04.01 2.2.13.1. Power-Up Calibration After device power-up, the I/O manager automatically initiates the calibration process. The process continues during device programming. 2.2.13.2. User Calibration The I/O PLL must be recalibrated for any of the following conditions after device power •...

  • Page 29: M-Series Clocking And Pll Design Considerations

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 30: Guidelines: Timing Closure

    You must verify that your design closes timing after dynamic reconfiguration or dynamic phase shift. • Intel recommends compiling the I/O PLL designs with each intended configuration setting to determine the variation in the clock with the I/O PLL settings. Related Information...

  • Page 31: Clocking Constraints

    Any SDC design constraints referring to the I/O PLL clocks must be listed after the SDC constraints for the IOPLL IP core. • Intel recommends reading the SDC for all I/O PLLs first in a design. You can do this by listing the IP before others in the file.

  • Page 32: Clock Control Intel Fpga Ip Core

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 33: Clock Control Intel Fpga Ip Core Ports And Signals

    Clock Multiplexing section, Quartus Prime Pro Edition User Guide: Design Recommendations Provides more information about the optimal clock multiplexing design. 4.3. Clock Control Intel FPGA IP Core Ports and Signals Table 6. Clock Control Intel FPGA IP Core Ports for M-Series Devices...
  • Page 34 769001 | 2024.04.01 Port Name Description Output of the Clock Control Intel FPGA IP core when Clock Divider option is not selected. outclk Clock enable of the clock gate block. This signal is active-high. Outputs of the Clock Control Intel FPGA IP core when the Clock Divider option is selected.

  • Page 35: Iopll Intel Fpga Ip Core

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 36: Iopll Ip Core Parameters - Pll Tab

    5. IOPLL Intel FPGA IP Core 769001 | 2024.04.01 5.2.1. IOPLL IP Core Parameters - PLL Tab Table 8. IOPLL IP Core Parameters - PLL Tab for M-Series Devices Parameter Value Description Device Family Agilex 7 Specifies the device family.
  • Page 37 5. IOPLL Intel FPGA IP Core 769001 | 2024.04.01 Parameter Value Description Number of Clocks 1–7 (fabric- Specifies the number of output clocks required for each device in the feeding), 1–4 PLL design. The requested settings for output frequency, phase shift, (I/O bank) and duty cycle are shown based on the number of clocks selected.

  • Page 38: Iopll Ip Core Parameters - Settings Tab

    5. IOPLL Intel FPGA IP Core 769001 | 2024.04.01 5.2.2. IOPLL IP Core Parameters - Settings Tab Table 9. IOPLL IP Core Parameters - Settings Tab for M-Series Devices Parameter Value Description PLL Auto Reset On or Off Automatically self-resets the PLL on loss of lock.

  • Page 39: Iopll Ip Core Parameters - Cascading Tab

    5. IOPLL Intel FPGA IP Core 769001 | 2024.04.01 5.2.3. IOPLL IP Core Parameters - Cascading Tab Table 10. IOPLL IP Core Parameters - Cascading Tab Parameter Value Description Connect to an upstream PLL On or Off Turn on to create an input port to enable destination (downstream) through Core clock Network PLL power-up calibration.

  • Page 40: Agilex 7 Clocking And Pll User Guide: M-Series Archives

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
  • Page 41 Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

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