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Intel altera Agilex 7 FPGA F Series User Manual
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Intel altera Agilex 7 FPGA F Series User Manual

Intel altera Agilex 7 FPGA F Series User Manual

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Development Kit User Guide
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7 FPGA F-Series
UG-20258
683024
2025.01.16

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Summary of Contents for Intel altera Agilex 7 FPGA F Series

  • Page 1 Explore more resources ® Altera Design Hub ™ Agilex 7 FPGA F-Series Development Kit User Guide 683024 Online Version Send Feedback 2025.01.16 UG-20258...

  • Page 2: Table Of Contents

    2.3.1. Installing the Quartus Prime Pro Edition Software...........7 2.3.2. Installing the Intel SoC EDS................ 8 2.3.3. Installing the Development Kit..............8 2.3.4. Installing the Intel FPGA Download Cable II Driver......... 9 3. Development Kit Setup....................10 3.1. Default Settings....................10 3.2. Powering Up the Development Kit................10 4.
  • Page 3 A. Development Kit Components..................36 A.1. Agilex 7 FPGA..................... 36 A.2. Configuration Support..................36 A.2.1. JTAG Chain and Header................36 A.2.2. On-board Intel FPGA Download Cable II .............37 A.3. Clocks........................ 38 A.4. Memory Interfaces....................39 A.5. Transceiver Interfaces..................39 A.6. HPS Interface......................39 A.7.

  • Page 4: Overview

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Block Diagram

    1.1. Block Diagram Figure 2. Agilex 7 FPGA F-Series Development Kit Block Diagram eMMC DIMM -CH1 RJ45 DIMM -CH0 MAX 10 DDR4 -HPS Conn DDR4/DDR-T Intel® FPGA Memory Download Cable UART JTAG JTAG Header Conn JTAG SW HPS_IOs I2C CTRL SD Card...

  • Page 6: Box Contents

    1. Overview 683024 | 2025.01.16 1.3. Box Contents • Agilex 7 FPGA F-Series development board • DDR4 DIMM module • USB2.0 Micro cable • Ethernet cable • 240 W power adapter and NA/EU/JP/UK cords • ATX power convert cable - 24 pin to 6 pin. Note: Only one DIMM module is provided with each development kit.

  • Page 7: Getting Started

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 8: Installing The Intel Soc Eds

    SoC embedded systems. As a part of the Intel SoC EDS, the Arm* Development Studio 5 (DS-5) Intel SoC FPGA Edition Toolkit provides a comprehensive set of embedded development tools for Altera's SoC FPGAs.

  • Page 9: Installing The Intel Fpga Download Cable Ii Driver

    Installation instructions for the Intel FPGA Download Cable II driver for your operating system are available on the Intel website. On the Intel website, navigate to the Cable and Adapter Drivers Information link to locate the table entry for your configuration and click the link to access the instructions.

  • Page 10: Development Kit Setup

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 11 3. Development Kit Setup 683024 | 2025.01.16 Running the Board in PCIe Socket as an Add-in Card Use the provided 240 W power adapter to supply power through . After the power adapter is plugged into and the board is plugged into the PCIe socket of the server or PC, the board powers up when the server or PC is powered.

  • Page 12: Board Test System

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 13: Setting Up The Quartus Prime Software For Bts Operation

    4. Board Test System 683024 | 2025.01.16 • C:\Program Files\Java\jre • C:\Program Files\Java\jfx Note: The unzipped folder name of JRE is (for example, jdk-11.0.xx+x-jre ). Rename it to jre. jdk-11.0.15+10-jre The unzipped folder name of JFX is . Rename it to jfx. javafx-sdk-17.0.2 2.
  • Page 14 4. Board Test System 683024 | 2025.01.16 Note: To ensure operating stability, keep the USB cable connected and the board powered on when running the demonstration application. The BTS cannot run correctly unless the USB cable is attached, and the board is on. To run the BTS, navigate to the <package dir>...

  • Page 15: Test The Functionality Of The Development Kit

    4. Board Test System 683024 | 2025.01.16 Figure 6. Linux Console Note: The or shell script checks the Java environment settings, copies .bat necessary files, and prompts if the environment is not set up correctly. The GUI displays the application tab corresponding to the design running in the FPGA.

  • Page 16: The Sys Info Tab

    4. Board Test System 683024 | 2025.01.16 Figure 7. The Configure Menu To configure the FPGA with a test system design, perform the following steps: 1. On the Configure menu, click the Configure command that corresponds to the functionality you wish to test. 2.

  • Page 17: Board Information

    4. Board Test System 683024 | 2025.01.16 Figure 8. The Sys Info Tab The following sections describe the controls on the System Info tab. Board Information The Board Information control displays static information about your board. • Board Name: Indicates the official name of the board given by the BTS. •...

  • Page 18: The Gpio Tab

    4. Board Test System 683024 | 2025.01.16 4.2.3. The GPIO Tab The GPIO tab allows you to interact with all the general-purpose user I/O (GPIO) components on your board. You can turn LEDs on or off and detect I C target devices connection status.

  • Page 19: The Qsfpdd Tab

    4. Board Test System 683024 | 2025.01.16 Figure 10. The GPIO Tab (for the Agilex 7 DK-DEV-AGF014EB Development Kit) The following sections describe the controls on the GPIO tab. User LEDs The User LEDs control displays the current state of the user LEDs. Toggle the LED buttons to turn the board LEDs on and off.
  • Page 20 4. Board Test System 683024 | 2025.01.16 Figure 11. The QSFPDD Tab The following sections describe controls in the QSFPDD tab. Status The Status control displays the following status information during the loopback test: • PLL Lock: Shows the PLL locked or unlocked state •...
  • Page 21 4. Board Test System 683024 | 2025.01.16 • Serial Loopback: Routes signals between the transmitter and the receiver. • VOD: Specifies the voltage output differential of the transmitter buffer. • Pre-emphasis tap: — Pre-tap 1: Specifies the amount of pre-emphasis on the first pre-tap of the transmitter buffer.

  • Page 22: Error Control

    4. Board Test System 683024 | 2025.01.16 Error Control This control displays data errors detected during analysis and allows you to insert errors: • Detected Errors: Displays the number of data errors detected in the received bit stream. • Inserted Errors: Displays the number of errors inserted into the transmit data stream.

  • Page 23: Performance Indicators

    4. Board Test System 683024 | 2025.01.16 Figure 14. The DDR4-0 Tab The following sections describe the controls on the DDR4-0 tab. Start Initiates DDR4 memory transaction performance analysis. Stop Terminates transaction performance analysis. Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start: •...

  • Page 24: The Ddr4-2 Tab

    4. Board Test System 683024 | 2025.01.16 • Detected Errors: Displays the number of data errors detected in the hardware. • Inserted Errors: Displays the number of errors inserted into the transaction stream. • Insert: Inserts a one-word error into the transaction stream each time you click the button.

  • Page 25: The Ddr4-3 Tab

    4. Board Test System 683024 | 2025.01.16 Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start: • Write, Read and Total performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve. •...
  • Page 26 4. Board Test System 683024 | 2025.01.16 Figure 16. The DDR4-3 Tab The following sections describe the controls on the DDR4-3 tab. Start Initiates DDR4 memory transaction performance analysis. Stop Terminates transaction performance analysis. Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start: •...

  • Page 27: Control On-Board Clock Through Clock Controller Gui

    4. Board Test System 683024 | 2025.01.16 • Detected Errors: Displays the number of data errors detected in the hardware. • Inserted Errors: Displays the number of errors inserted into the transaction stream. • Insert: Inserts a one-word error into the transaction stream each time you click the button.
  • Page 28 4. Board Test System 683024 | 2025.01.16 Figure 17. Clock Controller GUI The following sections describe the Clock Controller buttons. Read Reads the current frequency setting for the oscillator associated with the active tab. Default Sets the frequency for the oscillator associated with the active tab back to its default value.

  • Page 29: Related Information

    4. Board Test System 683024 | 2025.01.16 Import You can generate the register list from the Skyworks* ClockBuilder Pro tool and import it into Si5341 to update the settings of the RAM. Register changes are volatile after power cycling. Related Information •...

  • Page 30: Identify Test Pass Or Fail Based On Bts Gui Test Status

    4. Board Test System 683024 | 2025.01.16 Figure 18. Power Monitor GUI Temperature • Board: PCB surface temperature near • E-Tile/P-Tile/Core A/Core C: FPGA dies' internal TSD. • 0.9V/3.3V/1.8V: Regulator Related Information Running the BTS GUI on page 13 4.5. Identify Test Pass or Fail based on BTS GUI Test Status DDR4 DIMMs Plug the DDR4 DIMM module, which is shipped alone with this development kit, in .

  • Page 31: Development Kit Hardware And Configuration

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 32: Configure The Fpga Device By As Modes (Default Mode)

    5. Development Kit Hardware and Configuration 683024 | 2025.01.16 Related Information Agilex 7 Device Family Pin Connection Guidelines: F-Series and I-Series 5.2. Configure the FPGA Device by AS Modes (Default Mode) The default setting and system MAX 10 image support AS configuration mode. Power on and observe FPGA Configuration LED behavior.

  • Page 33: Custom Projects For The Development Kit

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 34: Document Revision History For The Agilex 7 Fpga F-Series Development Kit User Guide

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 35 7. Document Revision History for the Agilex 7 FPGA F-Series Development Kit User Guide 683024 | 2025.01.16 Document Changes Version 2023.11.30 • Added Figure: Power Tree (for the Agilex 7 DK-DEV-AGF014EB Development Kit—Power Solution • Added Figure: The GPIO Tab (for the Agilex 7 DK-DEV-AGF014EB Development Kit). •...

  • Page 36: Development Kit Components

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 37: On-Board Intel Fpga Download Cable Ii

    The JTAG chain allows programming of the Agilex 7 FPGA and the MAX 10 CPLD devices using the external Intel FPGA Download Cable II dongle. The dongle can be used to program both the Agilex 7 FPGA and MAX 10 CPLD via the external 2x5 pin 0.1"...

  • Page 38: Clocks

    This design converts USB data to interface with the Agilex 7’s dedicated JTAG port. Four LEDs are provided to indicate Intel FPGA Download Cable II activity. Two of them monitor the JTAG data-in and data-out signals; the remaining two monitor System Console activity.

  • Page 39: Memory Interfaces

    72-bit interfaces: DDR4 DIMM CH0, DDR4 DIMM CH1, DDR4 DIMM CH2, and DDR4 DIMM CH3. DDR4 DIMM CH1 is designed for HPS dedicated applications. The other three memory channels are for FPGA general usage and support both DDR4 and DDR-T (Intel ™ Optane PMem modules).

  • Page 40: General Input And Output

    A. Development Kit Components 683024 | 2025.01.16 A.7. General Input and Output A.7.1. Switches Table 6. SW1 Pin Connections SW1 Pin Board Label Function Default Settings MSEL0 Mode select 0 for SW1.1 configuration MSEL1 Mode select 1 for SW1.2 configuration MSEL2 Mode select 2 for SW1.3...

  • Page 41: Buttons

    JTAG Input Source ON: Select PCIe edge as SW4.1 JTAG master when external JTAG is absent. OFF: Select On-Board Intel FPGA Download Cable as JTAG master when external JTAG is absent. Power MAX 10 Bypass ON: Bypass the power MAX SW4.2...

  • Page 42: Leds

    Type Description PCIe reset PCIe Hard IP reset HPS warm reset Warm reset to HPS System MAX 10 reset On-board Intel FPGA Download Cable Reset A.7.3. LEDs Table 14. LEDs on the Development Kit Board Reference Schematic Signal Name Agilex 7 FPGA Pin Number I/O Standard 1.2V LVCMOS...
  • Page 43 A. Development Kit Components 683024 | 2025.01.16 Figure 22. Power Tree—Agilex 7 FPGA F-Series Development Kit (DK-DEV-AGF014EB) 1.5A x3 DDR-T 4 Phase FMC_VCC_EN LTC3884 + 102.5A / 19.2A 0.8V FMG_VCC/VCCP 0.8V 8.11A LTC3874 160A VID 0.013A VCCPLLDIG_HPS FLTR 12V_G1 0.9V 5.0A 2.7A 12V ATX 2x4...
  • Page 44 A. Development Kit Components 683024 | 2025.01.16 Figure 23. Power Tree—Agilex 7 FPGA F-Series Development Kit (DK-DEV-AGF014EA) 1.5A x3 DDR-T 4-phase U47,U48 8.FM6_VCC_EN ED8401 + 0.8V 102.5A/19.2A FM6_VCC/VCCP 0.8V ET6160 (x4) 8.11A 0.013A 160A FLTR VCCPLLDIG_HPS 0p9V_VCCH 5.0A 2.7A EM2140L VCCH ATX 2x4 12V_G1...
  • Page 45 A. Development Kit Components 683024 | 2025.01.16 Figure 24. Power Tree—Agilex 7 FPGA F-Series Development Kit (DK-DEV-AGF014E2ES) 1.5A x3 DDR-T 4-phase U47, U76, U77, U78, U79 FPGA_VCC_EN ED8401 + 0.8V 102.5A/19.2A FPGA_VCC/VCCP 0.8V 8.11A ET6160 160A VID 0p9V VCCH 5.0A 2.7A EM2140L VCCH...

  • Page 46: Power Sequence

    A. Development Kit Components 683024 | 2025.01.16 Figure 25. Power Tree—Agilex 7 FPGA F-Series Development Kit (DK-DEV-AGF014E3ES) 1.5A x3 DDR-T 4-phase U47, U48 FPGA_VCC_EN LTC3884 + 0.8V 102.5A/19.2A FPGA_VCC/VCCP 0.8V 8.11A LTC3874 160A VID 0p9V VCCH 5.0A 2.7A EM2140L VCCH 12V_G1 0.9V ATX 2x4...

  • Page 47: Power Measurement

    A. Development Kit Components 683024 | 2025.01.16 Table 15. Power Sequence Groups Group Number Voltage Rails Group1 VCC, VCCP, VCCL_HPS, VCCL_SDM, VCCH, VCC_HSSI_GXER, VCC_HSSI_GXPL, VCCH, VCCRT_GXER, VCCRT_GXPL Group2 VCCPT, VCCBAT, VCCH_GXER, VCCH_GXPL, VCCA_PLL VCCPLL_SDM, VCCADC, VCCPLL_HPS, VCCCLK_GXER Group3 VCCIO, VCCIO_SDM, VCCIO_HPS, VCCFUSEWR_SDM A.8.2.
  • Page 48 A. Development Kit Components 683024 | 2025.01.16 Figure 26. MAX6581 Temperature Sensor Circuit 3p3V_STBY C711 10Dpf C710 10Dpf OVERTEMPn R401 FPGA_TEMP0p DXP1 OVERT OVERTEMPn 41 Core A TSENSE_ALERTn R402 FPGA_TEMP0n ALERT DXN1 R730 FPGA_TEMP1p DXP2 Core C R731 FPGA_TEMP1n DXN2 R732 FPGA_TEMP2p DXP3...

  • Page 49: Developer Resources

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 50: Safety And Regulatory Compliance Information

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 51: Safety Warnings

    C. Safety and Regulatory Compliance Information 683024 | 2025.01.16 C.1.1. Safety Warnings Power Supply Hazardous Voltage AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply. Power Connect and Disconnect The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system.

  • Page 52: Power Cord Requirements

    C. Safety and Regulatory Compliance Information 683024 | 2025.01.16 Power Cord Requirements The plug on the power cord must be a grounding-type male plug designed for use in your region. It must have certification marks showing certification by an agency in your region.

  • Page 53: Cooling Requirements

    C. Safety and Regulatory Compliance Information 683024 | 2025.01.16 Cooling Requirements Maintain a minimum clearance area of 5 centimeters (2 inches) around the side, front and back of the board for cooling purposes. Do not block power supply ventilation holes and fan. Electro-Magnetic Interference (EMI) This equipment has not been tested for compliance with emission limits of FCC and similar international regulations.

  • Page 54: Electrostatic Discharge (Esd) Warning

    Failure to use wrist straps can damage components within the system. Attention: Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of this product in unsorted municipal waste.

  • Page 55: Compliance Information

    C. Safety and Regulatory Compliance Information 683024 | 2025.01.16 Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of product in unsorted municipal waste.

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