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Renesas RZ/G Series User Manual

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RZ/G3S Group

Renesas Microprocessor

RZ Family / RZ/G Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.1.10 Nov, 2023

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Summary of Contents for Renesas RZ/G Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.
Page 3 ® -M33 Note that after this page, they may be noted as Cortex-A55 and Cortex-M33 respectively. Examples of trademark or registered trademark used in the RZ/G series, 2nd Generation User’s Manual: Hardware; AMBA ® : AMBA is a registered trademark of Arm Limited.
Page 4 Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 5 Table of Contents Overview ........................72 Introduction ............................. 72 List of Specifications ........................73 1.2.1 CPU Core ..........................73 1.2.2 CPU Peripheral ........................74 1.2.3 Internal Memory ........................74 1.2.4 External Memory Interface ....................75 1.2.5 Sound Interface ........................76 1.2.6 Storage and Network ......................
Page 6 Register Descriptions ........................99 Description of Functions ....................... 100 3.4.1 Startup Sequence ......................100 3.4.2 Control by the SYSC ......................102 3.4.3 Warm Reset ........................103 3.4.4 Cortex-M33/Cortex-M33_FPU Sleep Mode ............... 104 3.4.5 SysTick Timers ........................107 3.4.6 Restrictions of Functions ....................108 Boot Mode .......................
Page 7 5.2.2 Cortex-M33/Cortex-M33_FPU Address Space ..............148 Accessible Areas .......................... 157 Bus System Control ........................159 5.4.1 Security Control ........................159 5.4.1.1 Re-Setting the Security Attribute Output from Bus Masters ........159 5.4.1.2 Determining the Security Levels of Bus Slaves ............161 5.4.2 Address Translation ......................
Page 8 6.3.25 ECCRAM1 Access Control Register (SYS_RAM1_EN) ............ 199 6.3.26 ECCRAM2 ECC Setting Register (SYS_RAM2_ECC) ............200 6.3.27 ECCRAM2 Access Control Register (SYS_RAM2_EN) ............ 200 6.3.28 ECCRAM3 ECC Setting Register (SYS_RAM3_ECC) ............201 6.3.29 ECCRAM3 Access Control Register (SYS_RAM3_EN) ............ 201 6.3.30 WDT0 Control Register (SYS_WDT0_CTRL) ..............
Page 9 6.3.66 SYS_AOF2 ......................... 228 6.3.67 SYS_AOF3 ......................... 229 6.3.68 SYS_AOF6 ......................... 230 6.3.69 SYS_AOF9 ......................... 231 6.3.70 SYS_LP_CTL1 ........................232 6.3.71 SYS_LP_CTL2 ........................234 6.3.72 SYS_LP_CTL5 ........................235 6.3.73 SYS_LP_CTL6 ........................237 6.3.74 SYS_LP_CTL7 ........................239 6.3.75 SYS_LP_CM33CTL0 ......................240 6.3.76 SYS_LP_CA55CK_CTL1 ....................
Page 10 7.2.4 Register Descriptions ......................270 7.2.4.1 PLLn (SSCG) Standby Control Register (CPG_PLLn_STBY) (n = 1, 4 or 6) ..270 7.2.4.2 PLLn (SSCG) Output Clock Setting Register 1 (CPG_PLLn_CLK1) (n = 1, 4 or 6) ......................272 7.2.4.3 PLLn (SSCG) Output Clock Setting Register 2 (CPG_PLLn_CLK2) (n = 1, 4 or 6) ......................
Page 11 7.2.4.51 Clock Control Register CANFD (CPG_CLKON_CANFD) ........339 7.2.4.52 Clock Control Register GPIO (CPG_CLKON_GPIO) ..........340 7.2.4.53 Clock Control Register ADC (CPG_CLKON_ADC) ..........341 7.2.4.54 Clock Control Register TSU (CPG_CLKON_TSU) ..........342 7.2.4.55 Clock Control Register AXI_ACPU_BUS (CPG_CLKON_AXI_ACPU_BUS) ..343 7.2.4.56 Clock Control Register AXI_MCPU_BUS (CPG_CLKON_AXI_MCPU_BUS) ..
Page 12 7.2.4.104 Clock Monitor Register TSU (CPG_CLKMON_TSU) ..........398 7.2.4.105 Clock Monitor Register AXI_ACPU_BUS (CPG_CLKMON_AXI_ACPU_BUS) ..399 7.2.4.106 Clock Monitor Register AXI_MCPU_BUS (CPG_CLKMON_AXI_MCPU_BUS) ..400 7.2.4.107 Clock Monitor Register AXI_COM_BUS (CPG_CLKMON_AXI_COM_BUS) ..402 7.2.4.108 Clock Monitor Register PERI_COM (CPG_CLKMON_PERI_COM) ...... 403 7.2.4.109 Clock Monitor Register REG1_BUS (CPG_CLKMON_REG1_BUS) .....
Page 13 7.2.4.157 Reset Control Register PERI_COM (CPG_RST_PERI_COM) ......459 7.2.4.158 Reset Control Register REG1_BUS (CPG_RST_REG1_BUS) ......460 7.2.4.159 Reset Control Register REG0_BUS (CPG_RST_REG0_BUS) ......461 7.2.4.160 Reset Control Register PERI_CPU (CPG_RST_PERI_CPU) ........ 462 7.2.4.161 Reset Control Register PERI_DDR (CPG_RST_PERI_DDR) ....... 463 7.2.4.162 Reset Control Register AXI_TZCDDR (CPG_RST_AXI_TZCDDR) ......
Page 14 7.2.4.210 eset Monitor Register PERI_DDR (CPG_RSTMON_PERI_DDR) ......515 7.2.4.211 Reset Monitor Register AXI_TZCDDR (CPG_RSTMON_AXI_TZCDDR) ....516 7.2.4.212 Reset Monitor Register OCTA (CPG_RSTMON_OCTA) ........517 7.2.4.213 Reset Monitor Register OTFDE_DDR (CPG_RSTMON_OTFDE_DDR) ....518 7.2.4.214 Reset Monitor Register OTFDE_SPI (CPG_RSTMON_OTFDE_SPI) ....519 7.2.4.215 Reset Monitor Register PDM (CPG_RSTMON_PDM) ...........
Page 15 Operating Procedures ........................591 7.4.1 Procedures for Supplying and Stopping Module Clocks............ 591 7.4.2 Procedures for Supplying and Stopping Reset Signals ............. 592 7.4.3 Procedure for Activating Modules ..................592 7.4.4 Procedures for PLL Setup ....................593 7.4.4.1 Procedure for Setting PLL Normal Mode (Changing the Output Clock and SSCG Mode) ............
Page 16 8.6.16 Bus Error Interrupt Status Control Register0 (BEISR0) ............. 635 8.6.17 Bus Error Interrupt Status Control Register1 (BEISR1) ............. 636 8.6.18 ECCRAM Error Interrupt Status Control Register0 (EREISR0) ......... 637 8.6.19 ECCRAM Error Interrupt Status Control Register1 (EREISR1) ......... 638 8.6.20 ECCRAM Error Interrupt Status Control Register0 (EREISR2) .........
Page 17 11.4 Initializing the ECC Function ......................673 11.5 Initializing the Detection-Usage Areas of the On-Chip RAM ............673 11.6 Usage Notes ..........................674 11.6.1 Notes on Setting the Registers of This Module ..............674 11.6.2 8- or 16-Bit Access ......................674 11.6.3 Numbers of Cycles for Reading from or Writing to a RAM Area with the ECC Function Enabled ..........................
Page 18 12.4.29 Non-Secure Response Transmission Interrupt Set Register (CA55 -> CM33) ....690 12.4.30 Non-Secure Response Transmission Interrupt Set Register (CM33_FPU -> CM33) ..690 12.4.31 Non-Secure Response Transmission Interrupt Clear Register (CM33_FPU -> CA55) ..691 12.4.32 Non-Secure Response Transmission Interrupt Clear Register (CM33 -> CA55) ....691 12.4.33 Non-Secure Response Transmission Interrupt Clear Register (CA55 ->...
Page 19 12.4.72 Secure Message Transmission Interrupt Clear Register (CM33 -> CM33_FPU) ....697 12.4.73 Secure Response Transmission Interrupt Status Register (CM33_FPU -> CA55) ... 698 12.4.74 Secure Response Transmission Interrupt Status Register (CM33 -> CA55) ....698 12.4.75 Secure Response Transmission Interrupt Status Register (CA55 -> CM33_FPU) ... 698 12.4.76 Secure Response Transmission Interrupt Status Register (CM33 ->...
Page 20 14.4.2 Next Destination Address Register n/nS (N0DA_n/nS, N1DA_n/nS) ........ 730 14.4.3 Next Transaction Byte Register n/nS (N0TB_n/nS, N1TB_n/nS) ........731 14.4.4 Current Source Address Register n/nS (CRSA_n/nS) ............732 14.4.5 Current Destination Address Register n/nS (CRDA_n/nS) ..........733 14.4.6 Current Transaction Byte Register n/nS (CRTB_n/nS) ............. 734 14.4.7 Channel Status Register n/nS (CHSTAT_n/nS) ..............
Page 21 14.8.2 Setting Example 2 (Register Mode/Software Request) ............. 803 14.8.3 Setting Example 3 (Register Mode/Continuous Execution) ..........805 14.8.4 Setting Example 4 (Link Mode) ..................807 14.8.5 Next Register Set Continuous Execution Setting .............. 810 15. System Counter (SYC) .................... 813 15.1 Overview ............................
Page 22 16.2.26 Timer Subcounters (TCNTSA and TCNTSB) ..............893 16.2.27 Timer Cycle Data Registers (TCDRA and TCDRB) ............893 16.2.28 Timer Cycle Buffer Registers (TCBRA and TCBRB) ............894 16.2.29 Timer Dead Time Data Registers (TDDRA and TDDRB) ..........894 16.2.30 Timer Dead Time Enable Registers (TDERA and TDERB) ..........895 16.2.31 Timer Buffer Transfer Set Registers (TBTERA and TBTERB) ..........
Page 23 16.5.1 Input/Output Timing......................1030 16.5.2 Interrupt Signal Timing ..................... 1036 16.6 Usage Note ..........................1039 16.6.1 Count Clock Restrictions ....................1039 16.6.2 Note on Cycle Setting ...................... 1039 16.6.3 Contention between TCNT Write and Clear Operations..........1040 16.6.4 Contention between TCNT Write and Increment Operations .......... 1040 16.6.5 Contention between TGR Write Operation and Compare Match ........
Page 24 17.2.1 Input Level Control/Status Register 1 (ICSR1) ..............1093 17.2.2 Input Level Control/Status Register 2 (ICSR2) ..............1094 17.2.3 Input Level Control/Status Register 3 (ICSR3) ..............1095 17.2.4 Input Level Control/Status Register 4 (ICSR4) ..............1097 17.2.5 Output Level Control/Status Register 1 (OCSR1) ............1099 17.2.6 Output Level Control/Status Register 2 (OCSR2) ............
Page 25 18.2.17 General PWM Timer Buffer Enable Register (GTBER) ........... 1176 18.2.18 General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register (GTITC) ......................1179 18.2.19 General PWM Timer Counter (GTCNT)................1182 18.2.20 General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F) ....1182 18.2.21 General PWM Timer Cycle Setting Register (GTPR) ............
Page 26 18.3.9.3 3-Phase Saw-Wave Complementary PWM Output with Automatic Dead Time Setting ........................1254 18.3.9.4 3-Phase Triangle-Wave Complementary PWM Output ........1255 18.3.9.5 3-Phase Triangle-Wave Complementary PWM Output with Automatic Dead Time Setting ......................1256 18.3.9.6 3-Phase Asymmetric Triangle-Wave Complementary PWM Output with Automatic Dead Time Setting ................
Page 27 19.4 Interrupt Sources ........................1309 19.5 External Trigger Output to the GPT .................... 1310 19.6 Usage Notes ..........................1311 19.6.1 Specifying Pins Associated with the GPT ................ 1311 20. General Timer (GTM) .................... 1312 20.1 Functional Overview ........................1312 20.1.1 Features of GTM ......................
Page 28 21.3.8 Parity Error Enable Register_n (PEER_n (n = 0, 1, 2)) ........... 1342 21.3.9 Parity Error Polarity Setting Register_n (PEPO_n (n = 0, 1, 2)) ........1343 21.3.10 Register Setting Order for Each WDT Channel ............... 1344 21.4 Operation ............................ 1345 21.4.1 WDT_CORE Operaton Timing ..................
Page 29 22.3.19 RTC Control Register 2 (RCR2) ..................1382 22.3.20 Time Error Adjustment Register (RADJ) ................1384 22.3.21 Time Capture Control Register (RTCCR0) ..............1385 22.3.22 Second Capture Register (RSECCP0)/BCNT0 Capture Register (BCNT0CP0) .... 1387 22.3.23 Minute Capture Register (RMINCP0) /BCNT1 Capture Register (BCNT1CP0) ....1388 22.3.24 Hour Capture Register (RHRCP0) /BCNT2 Capture Register (BCNT2CP0) ....
Page 30 23.2.9 Modulation Duty Register (MDDR) .................. 1424 23.2.10 FIFO Control Register (FCR) ................... 1427 23.2.11 FIFO Data Count Register (FDR) ..................1429 23.2.12 Serial Port Register (SPTR) ..................... 1430 23.2.13 Line Status Register (LSR) ....................1433 23.2.14 Serial Extended Mode Register (SEMR) ................. 1434 23.2.15 FIFO Trigger Control Register (FTCR) ................
Page 31 24.2.12 Modulation Duty Register (MDDR) .................. 1495 24.2.13 Serial Extended Mode Register (SEMR) ................. 1497 24.2.14 Noise Filter Setting Register (SNFR) ................1499 24.2.15 Extended function control register (SECR) ..............1500 24.3 Operation in Asynchronous Mode ....................1501 24.3.1 Serial Data Transfer Format .................... 1502 24.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode .....
Page 32 24.9.5 Restrictions on Clock Synchronous Transmission (Clock Synchronous Mode) ....1549 24.9.6 Restrictions on Using DMAC ................... 1551 24.9.7 Notes on Starting Transfer ....................1551 24.9.8 External Clock Input in Clock Synchronous Mode ............1551 24.9.9 Note on Transmit Enable Bit (TE bit) ................1551 24.10 IrDA Communications .........................
Page 33 25.3.17 I C Bus Shift Register (RIICnDRS) .................. 1599 25.4 Interrupt Sources ........................1600 25.5 Operation ............................ 1601 25.5.1 Communication Data Format ................... 1601 25.5.2 Initial Settings ........................1603 25.5.3 Master Transmit Operation ....................1604 25.5.4 Master Receive Operation ....................1608 25.5.5 Slave Transmit Operation ....................
Page 34 26.2 Registers ............................. 1654 26.2.1 List of Registers ....................... 1654 26.2.2 Protocol Selection Register (PRTS) ................. 1657 26.2.3 Bus Control Register (BCTL) ................... 1658 26.2.4 Master Device Address Register (MSDVAD) ..............1660 26.2.5 Reset Control Register (RSTCTL) ................... 1661 26.2.6 Present State Register (PRSST) ..................
Page 35 26.2.43 Bus Status Enable Register (BSTE) ................1718 26.2.44 Bus Interrupt Enable Register (BIE) ................. 1720 26.2.45 Bus Status Force Register (BSTFC) ................1722 26.2.46 Normal Transfer Status Register (NTST)................. 1724 26.2.47 Normal Transfer Status Enable Register (NTSTE) ............1730 26.2.48 Normal Transfer Interrupt Enable Register (NTIE) ............
Page 36 Overview .......................... 1936 26.5 Reset Descriptions ........................1938 26.6 Usage Notes ..........................1949 26.6.1 Settings for the Operating Clock ..................1949 27. Renesas Serial Peripheral Interface ..............1950 27.1 Features ............................1950 27.2 Input/Output Pins ........................1953 27.3 Register Descriptions ........................1954 27.3.1...
Page 37 27.4.7 Initialization ........................1990 27.4.8 SPI Operation ........................1991 27.4.9 Error Handling ........................2001 27.4.10 Loopback Mode ........................ 2002 27.4.11 Interrupt Sources ......................2002 28. Expanded Serial Peripheral Interface (xSPI) ............2003 28.1 Overview ............................. 2003 28.2 Input/Output Pins ........................2005 28.3 Register Descriptions ........................
Page 38 28.4.1 xSPI Bus .......................... 2047 28.4.1.1 Supported Protocol Mode ..................2047 28.4.1.2 xSPI Frame Interval ....................2052 28.4.1.3 xSPI Signals Timing Control ................. 2052 28.4.2 Manual-command ......................2056 28.4.2.1 Direct Mode ......................2056 28.4.2.2 Periodic Mode ....................... 2056 28.4.3 Memory-mapping ......................2057 28.4.3.1 Configuration ......................
Page 39 29.4.11 Device Memory Map Write Chip Select Timing Setting Register (DWCSTR) ....2096 29.4.12 Device Chip Select Timing Setting Register (DCSTR) ............ 2099 29.4.13 Controller and Device Setting Register (CDSR) .............. 2101 29.4.14 Memory Map Dummy Length Register (MDLR) .............. 2103 29.4.15 Memory Map Read/Write Command Register 0 (MRWCR0) ..........
Page 40 30.2.12 Global Control Register (CFDGCTR) ................2172 30.2.13 Global Status Register (CFDGSTS) ................2175 30.2.14 Global Error Flag Register (CFDGERFL) ................ 2177 30.2.15 Global TX Interrupt Status Register 0 (CFDGTINTSTS0 ) ..........2180 30.2.16 Global Timestamp Counter Register (CFDGTSC) ............2183 30.2.17 Global Acceptance Filter List Entry Control Register (CFDGAFLECTR) ......
Page 41 30.2.51 TX Message Buffer Transmission Completion Status Register n (CFDTMTCSTSn) (n = 0 to 3) ........................2245 30.2.52 TX Message Buffer Transmission Abort Status Register n (CFDTMTASTSn) (n = 0 to 3) ........................2247 30.2.53 TX Message Buffer Transmission Interrupt Enable Register n (CFDTMIECn) (n = 0 to 3) ........................
Page 42 30.2.90 Message Buffer Component Structure................2313 30.2.90.1 Start Addresses ....................2313 30.2.90.2 RX Message Buffer Component b (CFDRMBCPb[i]) ........... 2315 30.2.90.3 RX Message Buffer ID Register n (CFDRMIDn) (n = 0 to 31) ......2317 30.2.90.4 RX Message Buffer Pointer Register n (CFDRMPTRn) (n = 0 to 31) ....2318 30.2.90.5 RX Message Buffer CAN-FD Status Register n (CFDRMFDSTSn) (n = 0 to 31)......................
Page 43 30.4.1.5 Transmitter Delay Compensation ................. 2370 30.4.2 CAN Module Configuration after Hardware Reset ............2373 30.5 Acceptance Filtering Function using Global Acceptance Filter List (AFL) ......... 2375 30.5.1 Overview .......................... 2375 30.5.2 Allocation of AFL Entries to Each CAN Channel ............. 2377 30.5.3 AFL Entry Description ......................
Page 44 31. Gigabit Ethernet Interface ..................2441 31.1 Features ............................2441 31.1.1 Specification ........................2441 31.1.2 Block Diagram ........................2442 31.2 External signal pins ........................2443 31.3 Register Configuration ........................ 2444 31.3.1 Register Base Address ....................2444 31.3.2 IO Mode Registers ......................2444 31.3.3 DMAC Registers ......................
Page 45 31.4.1.37 Receive Interrupt Disable Register 3 (RID3) ............2489 31.4.1.38 Transmit Interrupt Status Register (TIS) ............... 2490 31.4.1.39 Transmit Interrupt Control Register (TIC) ............. 2493 31.4.1.40 Transmit Interrupt Enable Register (TIE) .............. 2495 31.4.1.41 Transmit Interrupt Disable Register (TID) ............. 2497 31.4.1.42 Common Interrupt Enable register (CIE) ..............
Page 46 31.4.2.46 MII Low Power parameter register 2 (LPTXMTH2) ..........2544 31.4.2.47 MII Low Power parameter register 3 (LPTXMTH3) ..........2545 31.4.2.48 MII Low Power parameter register 4 (LPTXMTH4) ..........2546 31.4.3 TOE Registers ........................2547 31.4.3.1 Checksum operating mode register (CSR0) ............2547 31.4.3.2 Tx Frame Checksum Enable register (CSR1) ............
Page 47 31.5.2 Descriptors ........................2598 31.5.2.1 Data Representation in URAM ................2598 31.5.2.2 Using Descriptor Chains in Queues ..............2599 31.5.2.3 Descriptor Base Address Table ................2600 31.5.2.4 Descriptor Chain Processing ................2601 31.5.2.5 Descriptor Interrupts ..................... 2601 31.5.2.6 Descriptor Type ..................... 2602 31.5.2.7 Layout of General Descriptors in the URAM............
Page 48 31.5.13 Configuration Procedure ....................2663 31.5.13.1 Set Up Procedure ....................2663 31.5.13.2 System Mode Change Procedure (Normal -> Network Standby) ......2665 31.5.13.3 System Mode Change Procedure (Network Standby -> Normal) ......2666 31.5.13.4 Stop Procedure ..................... 2667 31.5.14 Connection to PHY-LSI ....................2668 31.5.14.1 RGMII Frame Transmission/Reception Timing ............
Page 49 32A.1.2.2 Link Power Management (LPM) function.............. 2698 32A.1.2.3 OTG function ......................2699 32A.1.2.4 Battery-charging function ..................2699 32A.1.2.5 Suspend extension function .................. 2699 32A.1.3 Support of USB-Related Specifications ................2700 32A.2 Register Descriptions ........................2701 32A.2.1 Register Attributes......................2701 32A.2.2 Base Address ........................
Page 50 32A.8.3 Port Power (VBUS) control specifications................ 2793 32A.8.4 Timing Chart for Overcurrent Detection and Recovery ............ 2794 32A.9 Procedure for Setting this Module ....................2795 32A.9.1 Host/Peripheral Common Setting Sequence ..............2795 32A.9.2 Initialization Sequence ..................... 2796 32A.9.3 Flow of Error Handling ..................... 2797 32B.
Page 51 32B.2.8.1 Interrupt Enable Register 0 [INTENB0] <Address: H’030> ........2824 32B.2.8.2 BRDY Interrupt Enable Register [BRDYENB] <Address: H’036> ......2825 32B.2.8.3 NRDY Interrupt Enable Register [NRDYENB] <Address: H’038> ......2826 32B.2.8.4 BEMP Interrupt Enable Register [BEMPENB] <Address: H’03A> ....... 2827 32B.2.9 SOF Control Register .......................
Page 52 32B.2.17.2 PIPE1 Transaction Counter Register [PIPE1TRN] <Address: H’092> PIPE2 Transaction Counter Register [PIPE2TRN] <Address: H’096> PIPE3 Transaction Counter Register [PIPE3TRN] <Address: H’09A> PIPE4 Transaction Counter Register [PIPE4TRN] <Address: H’09E> PIPE5 Transaction Counter Register [PIPE5TRN] <Address: H’0A2> ....2873 32B.2.18 Low Power Control Register .................... 2875 32B.2.18.1 Low Power Control Register [LPCTRL] <Address: H’100>...
Page 53 32B.5.2.1 Channel Control Register ch0 [CHCTRL_0] <Address: H’428> Channel Control Register ch1 [CHCTRL_1] <Address: H’468> ......2894 32B.5.3 Channel Configuration Register ..................2897 32B.5.3.1 Channel Configuration Register ch0 [CHCFG_0] <Address: H’42C> Channel Configuration Register ch1 [CHCFG_1] <Address: H’46C> ....2897 32B.5.4 Channel Interval Register n .....................
Page 54 32B.9.1 System Control and Oscillation Control ................2915 32B.9.1.1 USB data bus resistor control ................2915 32B.9.2 Interrupt Function ......................2916 32B.9.2.1 Overview of Interrupt Function (other than DMA Master) ........2916 32B.9.2.2 Device State Transition Interrupts ................ 2918 32B.9.2.3 Control Transfer Stage Transition Interrupts ............
Page 55 32B.9.15 Arbitration between DMACs ..................... 2977 32B.9.16 Notes ..........................2978 32B.9.16.1 Access ........................2978 32B.9.16.2 Level Interrupt bit ....................2978 33. SD/MMC Host Interface..................2979 33.1 Overview ............................. 2979 33.1.1 Features ........................... 2979 33.1.2 External Pins ........................2981 33.1.3 Register Configuration ..................... 2982 33.2 Register Description ........................
Page 56 33.3 Operation ............................ 3019 33.3.1 SD Interface ........................3019 33.3.2 Card Detect/Write Protect ....................3023 33.3.3 Interrupt Request ......................3025 33.3.4 Communications Errors and Timeouts................3026 33.4 Usage Example .......................... 3028 33.4.1 Command without Data Transfer ..................3028 33.4.2 Single Block Read ......................3031 33.4.3 Single Block Write ......................
Page 57 34.1.2 External Pins ........................3076 34.1.3 Block Diagram ........................3076 34.1.4 Reset ..........................3077 34.1.4.1 Reset Sequence for Power-On Reset ..............3077 34.2 Register Configuration ........................ 3078 34.2.1 Register Type ........................3078 34.2.2 Register List ........................3079 34.2.2.1 AXI Bridge Registers..................... 3080 34.2.2.2 PCI Express Configuration Registers (Type1) ............
Page 58 34.3.1.41 DMA Interrupt Vector 1 Registers (Offset: H’4D4) ..........3137 34.3.1.42 MSI Receive Enable n Registers (Offset: H’6x0) ..........3138 34.3.1.43 MSI Receive Message Data n Registers (Offset: H’6x4) ........3139 34.3.1.44 MSI Receive Mask n Registers (Offset: H’6x8) ............ 3140 34.3.1.45 MSI Receive Status n Registers (Offset: H’6xC) ..........
Page 59 34.3.1.77 PCIe Window Mask (Lower) Registers (H’1000 + Offset: H’108/H’128/H’148/…/H’1E8) ........... 3169 34.3.1.78 PCIe Window Mask (Upper) Registers (H’1000 + Offset: H’10C/H’12C/H’14C/…/H’1EC) ..........3170 34.3.1.79 PCIe Destination (Lower) Registers (H’1000 + Offset: H’110/H’130/H’150/H’170/…/H’1F0) ........3171 34.3.1.80 PCIe Destination (Upper) Register (H’1000 + Offset: H’114/H’134/H’154/H’174/…/H’1F4) ........
Page 60 34.3.2.45 Root Error Command (Offset: H’612C)..............3226 34.3.2.46 Root Error Status (Offset: H’6130) ................ 3227 34.3.2.47 Error source Identification Register (Offset: H’6134) ..........3228 34.3.2.48 Device Serial Number Extended Capability (Offset: H’6150) ....... 3228 34.3.2.49 Serial Number Register (Lower DW) (Offset: H’6154) .......... 3229 34.3.2.50 Serial Number Register (Upper DW) (Offset: H’6158) ..........
Page 61 34.5.1.2 De-asserting the Reset ..................3281 34.5.1.3 Checking if the Link is Up ..................3282 34.5.2 Setting the Windows (Root Complex Mode) ..............3283 34.5.2.1 AXI Window Setting ....................3284 34.5.2.2 PCIe Window Setting .................... 3286 34.5.2.3 Device Search ....................... 3287 34.5.3 Setting the PCIe Address Space ..................
Page 62 35.5.1 Operational State ......................3367 35.5.1.1 Idle State ....................... 3367 35.5.1.2 Communication States ..................3370 35.5.2 Communication Operation ....................3374 35.5.2.1 Start Communication .................... 3375 35.5.2.2 Transmission ......................3376 35.5.2.3 Reception ......................3378 35.5.2.4 Transmission and Reception ................3379 35.5.2.5 Halt Communication ....................
Page 63 36.5.4 Note on Access while the SRC is Operating ..............3414 36.5.5 Note on After rest ......................3414 37. PDM Interface (PDM) .................... 3415 37.1 Overview ............................. 3415 37.1.1 Feature ..........................3415 37.1.2 Block Diagram ........................3416 37.1.3 External Pins ........................3417 37.1.4 Connected Unit ........................
Page 64 37.2.2.29 Short Circuit Threshold Setting Register Channel n (PDMm_PDSCTSRCHn) (m = 0) ........................3455 37.2.2.30 Overvoltage Lower Threshold Register Channel n (PDMm_PDOVLTRCHn) (m = 0) ........................3456 37.2.2.31 Overvoltage Upper Threshold Register Channel n (PDMm_PDOVUTRCHn) (m = 0) ........................3457 37.2.2.32 Data Read Control Register Channel n (PDMm_PDDRCRCHn) (m = 0) ....
Page 65 38. Renesas SPDIF Interface ..................3501 38.1 Overview ............................. 3501 38.2 Features ............................3501 38.3 Functional Block Diagram ......................3502 38.4 Input/Output Pins ........................3502 38.5 Renesas SPDIF (IEC60958) Frame Format................3503 38.6 Register............................3505 38.7 Register Descriptions ........................3506 38.7.1...
Page 66 39.2 List of Registers .......................... 3534 39.3 Register Descriptions ........................3535 39.3.1 A/D Converter Mode Register 0 (ADM0) ................. 3535 39.3.2 A/D Converter Mode Register 1 (ADM1) ................. 3537 39.3.3 A/D Converter Mode Register 2 (ADM2) ................. 3539 39.3.4 A/D Converter Mode Register 3 (ADM3) ................. 3540 39.3.5 TSU Conversion Mode Register (TSUMODE) ..............
Page 67 40.1.2 Block Diagram ........................3581 40.1.2.1 APB_REG ......................3581 40.1.2.2 Thermal Sensor ....................3581 40.1.3 External Pins ........................3582 40.1.4 Interrupts .......................... 3582 40.2 Register Configuration ........................ 3583 40.2.1 List of Register ......................... 3583 40.3 Register Descriptions ........................3584 40.3.1 Sensor Mode Register (TSU_SM) ...................
Page 68 Battery Backup Function ....................3626 42.4.2 Tamper Detctor ........................ 3627 42.4.3 Isolation Control ....................... 3629 42.4.4 Interrupt ..........................3629 43. Renesas Secure IP (RSIP-E05A) ................3630 43.1 Overview ............................. 3630 43.2 Operation ............................ 3633 43.2.1 Encryption Engine ......................3633 43.2.2 Encryption and Decryption ....................
Page 69 45.1.5 Special Purpose Port Configuration ................. 3644 45.2 Register Configuration ........................ 3651 45.2.1 Port Register (P_m) ......................3651 45.2.2 Port Mode Register (PM_m) .................... 3652 45.2.3 Port Mode Control Register (PMC_m) ................3652 45.2.4 Port Function Control Register (PFC_m) ................. 3653 45.2.5 Port Input Register (PIN_m) .....................
Page 70 45.3.20 I3C Control Register (I3C_SET) ..................3690 45.3.21 XSPI/OCTA Output Enable Control Register (XSPI/OCTA Hi-Z) ........3691 45.4 Operation ............................ 3692 45.4.1 Operation for GPIO Function ................... 3692 45.4.2 Operation for Peripheral Function ..................3692 46. Debug Interface ..................... 3693 46.1 Overview .............................
Page 71 47.5.17 Serial Communications Interface with FIFO (SCIFA) Access Timing ......3758 47.5.18 Serial Communications Interface (SCIg) Access Timing ..........3760 47.5.19 Renesas Serial Peripheral Interface (RSPI) Access Timing ..........3762 47.5.20 A/D Converter Access Timing ..................3765 47.5.21 Watchdog Timer Access Timing ..................3765 47.5.22 PDM Interface Access Timing ..................
Page 72 RZ/G3S Group 1. Overview Overview Introduction This LSI is a single-chip microprocessor that includes a single Arm ® Cortex ® -A55 core, which operates at speeds of up to 1.1GHz and two Cortex -M33 250MHz cores. One Cortex -M33 has FPU function. This LSI includes a 32-Kbyte ®...
Page 73 RZ/G3S Group 1. Overview List of Specifications 1.2.1 CPU Core Item Description ● System CPU Cortex-A55 Arm Cortex-A55 Single Core 1.1 GHz ● L1 I-cache: 32 Kbytes (Parity) / D-cache : 32 Kbytes (ECC) ● L2 cache: Not included ● L3 cache: 256 Kbytes (ECC) ●...
Page 74 RZ/G3S Group 1. Overview 1.2.2 CPU Peripheral Item Description ● Clock Pulse Generator Generates the clocks from external clock (EXCLK 24 MHz). (CPG) Maximum Arm Cortex-A55 clock: 1.1 GHz Maximum Arm Cortex-M33 clock: 250 MHz Maximum DDR clock: 800 MHz (DDR4-1600 / LPDDR4-1600) Maximum AXI-bus clock: 200 MHz Maximum APB-bus clock: 100 MHz ●...
Page 75 RZ/G3S Group 1. Overview 1.2.4 External Memory Interface Item Description ● External Bus Controller for DDR4 Support DDR4-1600 / LPDDR4-1600 / LPDDR4 SDRAM ● Bus Width: 16-bit (DDR) ● In line ECC supported (Support error detection interrupt) ● Memory Size: Up to 4 Gbytes (DDR4), 1 Gbytes (LPDDR4) ●...
Page 76 RZ/G3S Group 1. Overview 1.2.5 Sound Interface Item Description ● Serial Sound Interface 4 channels bidirectional serial transfer (SSI) ● 2 external clock sources available ● Full Duplex communication ● Support of I2S / Monaural / TDM audio formats ● Support of master and slave functions ●...
Page 77 RZ/G3S Group 1. Overview 1.2.6 Storage and Network Item Description ● USB2.0 Host / Function 2 channels (ch0: Host-Function ch1: Host only) (USB) ● Compliance with USB2.0 ● Supports On-The-Go (OTG) Function ● Supports Battery Charging Function ● Internal dedicated DMA ●...
Page 78 RZ/G3S Group 1. Overview 1.2.7 Timer Item Description ● Multi-function Timer Pulse Unit 3 9 channels (16 bits × 8 channels, 32 bits × 1 channel) (MTU3a) ● Module clock frequency: 100 MHz ● Maximum 28 lines of pulse inputs/outputs and 3 lines of pulse inputs ●...
Page 79 RZ/G3S Group 1. Overview Item Description ● Watchdog Timer 3 channels (WDT) ● A counter overflow can reset the LSI ● CPU parity error can reset the LSI ● General Timer 32 bits × 8 channels (GTM) ● Two operating modes –...
Page 80 ● Modem control function ● Encoding and decoding of IrDA communications waveforms in accord with version 1.0 of the IrDA standard (on channel 0) ● Renesas Serial Peripheral 5 channels Interface (RSPI) ● SPI operation ● Master mode and slave mode supported ●...
Page 81 RZ/G3S Group 1. Overview 1.2.9 Security Item Description ● Renesas Security IP (RSIP-E01B) Security algorism [option] – Common key encryption: AES (compliant with NIST FIPS PUB 197) – Non-common key encryption: RSA, ECC ● Other features – TRNG (true-random number generator) –...
Page 82 RZ/G3S Group 1. Overview 1.2.12 Power Supply Voltage Item Description ● Power supply voltage VBATT_VDD: 1.50 to 1.95 V ● VDD, PLL16_AVDD, PLL23_AVDD, PLL4_AVDD: 0.905 to 0.99 V ● PVDD33: 3.0 to 3.6 V ● PVDD18, ADC_AVDD18, OTP_AVDD18: 1.65 to 1.95 V ●...
Page 83 RZ/G3S Group 1. Overview Product Lineup Table 1.1 Product Lineup Group Package Part Number Security PCIe RZ/G3S 14 mm BGA R9A08G045S37GBG 1 × Cortex-A55, 2 × Cortex-M33 Available Available R9A08G045S17GBG 1 × Cortex-A55, 1 × Cortex-M33 R9A08G045S33GBG 1 × Cortex-A55, 2 × Cortex-M33 Not supported R9A08G045S13GBG 1 ×...
Page 84 RZ/G3S Group 2. System CPU Cortex-A55 System CPU Cortex-A55 The Cortex-A55 system CPU is a core block equipped with single Cortex-A55 core. For details on the functions including interrupts of the Cortex-A55, see the Arm ® Cortex ® -A55 Core Technical Reference Manual and related documents in Section 2.4, Function Reference.
Page 85 RZ/G3S Group 2. System CPU Cortex-A55 Resets Table 2.3 shows the supported types of reset and the areas that are reset by the respective types. For the procedures of handling the individual resets, see Section 2.2.1, Cold Reset and the subsequent parts. See the Arm ®...
Page 86 RZ/G3S Group 2. System CPU Cortex-A55 2.2.1 Cold Reset A cold reset is applied at any of the following cases. (a) The sequence of a power-on reset by the CPG is executed. (b) The WDT counter has overflowed or a non-correctable error has been detected. (c) Software control by the Cortex-M33 system CPU is applied.
Page 87 RZ/G3S Group 2. System CPU Cortex-A55 To release cold reset and start core 0 by case c reset, follow the procedure below. Write Register: CPG_CLUSTER_PCHCTL Set H’0048_0001 Write Register: CPG_CORE0_PCHCTL Set H’0008_0001 Write Register: CPG_RST_CA55 Set H’1FFF_1C00 Read Register: CPG_RSTMON_CA55 Confirm H’0000_03FF Write Register: CPG_RST_CA55 Set H’1FFF_1FF7...
Page 88 RZ/G3S Group 2. System CPU Cortex-A55 2.2.2 Core Warm Reset There are the two types of core warm reset: internal and external resets. The former requires software control by the Cortex-A55 system CPU itself and the latter requires software control by the Cortex-A55 and Cortex-M33 system CPUs.
Page 89 RZ/G3S Group 2. System CPU Cortex-A55 To apply an external reset to core 0, follow the procedure below. Execute power-down sequence for core0 ® (For detial, see Arm -A55 Core Technical Reference Manual) Write Register: CPG_CORE0_PCHCTL Set H’0000_0001 or H’0001_0001 Read Register: CPG_CORE0_PCHMON Confirm H’0000_0001 Write Register: CPG_CORE0_PCHCTL...
Page 90 RZ/G3S Group 2. System CPU Cortex-A55 To release core 0 from the core warm reset state and start the core, follow the procedure below. Write Register: CPG_CORE0_PCHCTL Set H’0008_0001 Write Register: CPG_RST_CA55 Set H’1FFF_1FFF Read Register: CPG_RSTMON_CA55 Confirm H’0000_0000 Read Register: CPG_CORE0_PCHMON Confirm H’0000_0001 Write Register: CPG_CORE0_PCHCTL Set H’0008_0000...
Page 91 RZ/G3S Group 2. System CPU Cortex-A55 2.2.3 Cluster Warm Reset This reset requires software control by the Cortex-A55 and Cortex-M33 system CPUs. To apply this reset for core0, follow the procedure below. 1. Execute power-down sequence for core0 2. Write Register: CPG_CORE0_PCHCTL Set H’0000_0001 or H’0001_0001 3.
Page 92 RZ/G3S Group 2. System CPU Cortex-A55 To release from the cluster warm reset state and start core 0, follow the procedure below. Write Register: CPG_CLUSTER_PCHCTL Set H’0048_0001 Write Register: CPG_CORE0_PCHCTL Set H’0008_0001 Write Register: CPG_RST_CA55 Set H’1FFF_1FF7 Read Register: CPG_RSTMON_CA55 Confirm H’0000_0008 Read Register: CPG_CLUSTER_PCHMON Confirm H’0000_0001...
Page 93 RZ/G3S Group 2. System CPU Cortex-A55 2.2.4 Debug Reset Debug resets can only be applied under software control. To apply a debug reset, follow the procedure below. Write Register: CPG_RST_CA55 Set H’1FFF_0FFF Read Register: CPG_RSTMON_CA55 Confirm H’0000_1000 To release from the debug reset state, follow the procedure below. Write Register: CPG_RST_CA55 Set H’1FFF_1FFF Read Register: CPG_RSTMON_CA55...
Page 94 RZ/G3S Group 2. System CPU Cortex-A55 Low Power Consumption Mode 2.3.1 Cortex-A55 Sleep Mode Cortex-A55 Sleep Mode of this LSI is a low power consumption mode obtained by having a core execute the WFI instruction. For details on the WFI instructions, see the Arm ®...
Page 95 RZ/G3S Group 2. System CPU Cortex-A55 Function Reference For details on the functions of the DynamIQ™ Shared Unit and Cortex-A55, see the documents listed below. ● ® DynamIQ Shared Unit Technical Reference Manual ® Cortex ® -A55 Core Technical Reference Manual ●...
Page 96 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU System CPU Cortex-M33/Cortex-M33_FPU This LSI has the Cortex-M33 system CPU and the Cortex-M33_FPU system CPU. The Cortex-M33 system CPU is a core block equipped with an Arm Cortex-M33 processor without floating-point. The Cortex-M33_FPU system CPU is a core block equipped with an Arm Cortex-M33 processor with floating-point. The Cortex‑M33 processor is a highly energy-efficient processor that is intended for a microcontroller and deeply embedded applications.
Page 97 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU 3.1.1 Interrupts Table 3.2 Cortex-M33 System CPU Interrupt Name Description Type Active Level CTIIRQ [1:0] CTI interrupt output Level High Table 3.3 Cortex-M33_FPU System CPU Interrupts Name Description Type Active Level CTIIRQ [1:0] CTI interrupt output Level High FPIXC...
Page 98 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU Address Space For details on the address space, refer to the Arm ® Cortex ® -M33 Processor Technical Reference Manual. 3.2.1 IDAU Setting The Cortex-M33/Cortex-M33_FPU system CPU uses the IDAU. Table 3.4 shows the security attributes assigned by the IDAU.
Page 99 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU Register Descriptions For details on registers, refer to the Arm ® Cortex ® -M33 Processor Technical Reference Manual. For the device-specific Cortex-M33/Cortex-M33_FPU system CPU control registers, see the section on the system controller (SYSC). R01UH1014EJ0110 Rev.1.10 Page 99 of 3776...
Page 100 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU Description of Functions For the registers and functions of Cortex-M33/Cortex-M33_FPU, refer to the Arm ® Cortex ® -M33 Processor Technical Reference Manual and Arm ® v8-M Architecture Reference Manual. 3.4.1 Startup Sequence The startup sequence of the Cortex-M33/Cortex-M33_FPU system CPU is shown in the figure below. It is designed to execute by other processor (Cortex-A55) for the function and sequence of Cortex-M33/Cortex- M33_FPU control here.
Page 101 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU Start Confirm the SSC setting Registers: SYS_CM33FPU_CFG0/1 Registers: SYS_CM33FPU_CFG0/1 Set H’0101_2E1E Set H’0001_312C Registers: SYS_CM33FPU_CFG2/3 Set the vector address. Registers: CPG_CLKON_CM33 Set H’0100_0100 Registers: CPG_CLKMON_CM33 Register Read. CLK is ON Registers: CPG_RST_CM33 Set H’0400_0400 Registers: CPG_RST_CM33 Set H’0700_0700 Registers: CPG_RSTMON_CM33...
Page 102 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU 3.4.2 Control by the SYSC In this LSI, the system controller (SYSC) is used to control the functions of the Cortex-M33/Cortex-M33_FPU system CPU. For details of SYSC registers, see the section on the system controller (SYSC). Table 3.5 List of Functions Controlled by the SYSC Description...
Page 103 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU 3.4.3 Warm Reset When executing a warm reset, the WFI instruction is used to guarantee that no transaction is issued. The warm reset sequence is shown below. For a details of SYSC registers, see the section on the system controller (SYSC).
Page 104 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU 3.4.4 Cortex-M33/Cortex-M33_FPU Sleep Mode In this LSI, the sleep mode for the Cortex-M33/Cortex-M33_FPU system CPU is Cortex-M33/Cortex-M33_FPU Sleep Mode. In this mode, some modules (SysTick timers, NVIC, etc.) of the core can operate. The following procedure is the example sequence of a transition to Cortex-M33/Cortex-M33_FPU Sleep Mode. User Software SYSC Cortex-M33...
Page 105 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU User Software SYSC Cortex-M33_FPU (for Cortex-M33_FPU) Slow down the speed of Cortex-M33_FPU clock Write SYS_LP_CTL7.IM33FPU_MASK = 1 Mask CM33_FPU interrupt Set the return factor to NVIC Issue Barrier Instruction Write SCR.SLEEPDEEP = 1 Set Deep Sleep Mode Confirm setting of Read SCR.SLEEPDEEP == 1 SLEEPDEEP bit...
Page 106 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU (8) Return from Cortex-M33/Cortex-M33_FPU Sleep Mode when the event occurs or the interrupt set in NVIC occurs. (9) Confirm the interrupt cause and perform the processing required for returning from Cortex-M33/Cortex- M33_FPU Sleep Mode.* (10) And then clear the interrupt cause.* (11) Set the interrupt causes for the normal operation to NVIC.* (12) Recover the speed of Cortex-M33/Cortex-M33_FPU clock.*...
Page 107 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU 3.4.5 SysTick Timers The SysTick timers in the Cortex-M33/Cortex-M33_FPU are described below. There is one Secure SysTick timer and one Non-secure SysTick timer. ● The count cycle of SysTick timers is common to Secure and Non-secure. ●...
Page 108 RZ/G3S Group 3. System CPU Cortex-M33/Cortex-M33_FPU 3.4.6 Restrictions of Functions The Cortex-M33 system CPU has some restrictions on the functions due to specification of this LSI. Table 3.6 lists the restrictions on the functions. Table 3.6 List of Restrictions of Functions Description WFE instruction is not supported in a warm reset.
Page 109 RZ/G3S Group 4. Boot Mode Boot Mode Overview This LSI has two cold boots and four boot modes. Boot mode 0: Booting from 3.3-V eSD* Boot mode 1: Booting from 1.8-V/3.3-V eMMC* Boot mode 2: Booting from the 1.8-V/3.3-V Single, Quad, or Octal* serial flash memory Boot mode 3: Booting from the program downloaded through the serial communications with FIFO (SCIF) Note 1.
Page 110 RZ/G3S Group 4. Boot Mode Table 4.3 Boot Device I/F Voltage Setting Pin Signal Name Function Description MD_BOOT2 Boot Device I/F Voltage Boot Device I/F Voltage Settings Settings This pin is valid only for boot mode 1 (eMMC) and boot mode 2 (Serial Flash Memory) 0: 3.3 V 1: 1.8 V...
Page 111 RZ/G3S Group 4. Boot Mode Operation 4.2.1 Boot Mode 0 (eSD) Table 4.4 shows the interface signals used for connection with the external device in boot mode 0 (eSD). This LSI supports the embedded SD (eSD) defined in the SD Specification Part 1 eSD Addendum (Version 2.10). Table 4.4 External Interface Signals Used in Boot Mode 0 Interface Module...
Page 112 RZ/G3S Group 4. Boot Mode 4.2.1.1 External Connections Figure 4.1 shows the connections with the eSD device. This LSI Embedded SD (eSD) SD0_CLK SD0_PVDD SD0_CMD SD0_PVDD SD0_DATA0~3 SD0_PVDD SD0_DATA4~7 PVDD SD0_CD PVDD SD0_WP SD0_RST# open Figure 4.1 Connections in Boot Mode 0 R01UH1014EJ0110 Rev.1.10 Page 112 of 3776...
Page 113 RZ/G3S Group 4. Boot Mode 4.2.1.2 Overview of Operation This mode is used to boot this LSI from the user program stored in the eSD device. The operating voltage is set to 3.3 V and the width of the data bus connected to the eSD device is fixed to four bits in this mode. SDHI0 used as the interface controller in this mode is placed in the module standby mode at the startup of the LSI.
Page 114 RZ/G3S Group 4. Boot Mode 4.2.1.4 Allocation of the Loader Programs in the eSD Device (1) Allocation in eSD V2.0 (Single Partition) Figure 4.2 shows the allocation of the loader program size blocks and loader programs in the eSD device conforming to the eSD V2.0 standard.
Page 115 RZ/G3S Group 4. Boot Mode eSD V2.0 Physical Partition #0 Sector 0 Unused area Sector 1 Loader program size block #0 Sector 2 Loader program size block #1 (reserved area) Order of search for loader program size block Note: Transfer of the loader program size block always begins from area #0 (sector 1).
Page 116 RZ/G3S Group 4. Boot Mode +H’04 +H’04 +H’00 Loader program data size (4 bytes) Loader program load address (4 bytes) Loader program Destination address (4 bytes) Don’t Care bytes +H’1FE +H’1FE H’55 H’AA Signature Figure 4.3 Structure of the Loader Program Size Block NOTE The loader program data size, loader program load address, and loader program destination address are expected to be stored in 4-byte little-endian.
Page 117 RZ/G3S Group 4. Boot Mode (2) Allocation in eSD V2.1 (Multi Partitions) Figure 4.4 shows the allocation of the loader program size blocks and loader programs in the eSD device conforming to the eSD V2.1 standard. To prevent read-disturb errors, up to seven loader program size blocks and loader programs can be multiplexed and written to the eSD device The specifications and allocation of loader program size blocks are the same as those in eSD V2.0.
Page 118 RZ/G3S Group 4. Boot Mode eSD V2.1 Physical Partition #1 Sector 0 Unused area Sector 1 Loader program size block #0 Sector 2 Loader program size block #1 (reserved area) Order of search for loader program size block Note: Transfer of the loader program size block always begins from area #0 (sector 1).
Page 119 RZ/G3S Group 4. Boot Mode (3) How to Distinguish between eSD V2.0 (Single Partition) and V2.1 (Multi Partitions) This boot program first assumes that an eSD device supporting multi partitions is connected and begins loader program transfer from physical partition #1. If an error regarding a command for multi partitions shown in the following table occurs, the boot program assumes that an eSD device with a single partition is connected and transfers the loader program from physical partition #0.
Page 120 RZ/G3S Group 4. Boot Mode 4.2.2 Boot Mode 1 (1.8-V / 3.3-V eMMC) Table 4.6 shows the interface signals used for connection with the external device in boot mode 1 (eMMC). This LSI supports the eMMC that operates in the boot operation mode prescribed in JEDEC STANDARD JESD84 A44 (MMCA 4.4).
Page 121 RZ/G3S Group 4. Boot Mode 4.2.2.1 External Connections Figure 4.5 shows the connections with the eMMC device. The boot program in this LSI does not monitor the state of the SD0_CD and SD0_WP pins. This LSI eMMC SD0_PVDD = 1.8 V or 3.3 V SD0_CLK SD0_PVDD SD0_CMD...
Page 122 RZ/G3S Group 4. Boot Mode 4.2.2.2 Overview of Operation This mode is used to boot this LSI from the user program stored in the eMMC device. The operating voltage is set to 1.8 V or 3.3 V and the width of the data bus connected to the eMMC device is fixed to eight bits in this mode. SDHI0 used as the interface controller in this mode is placed in the module standby mode at the startup of the LSI.
Page 123 RZ/G3S Group 4. Boot Mode 4.2.2.4 Allocation of the Loader Program in the eMMC Device Figure 4.6 shows the allocation of the loader program in the eMMC device conforming to the MMCA 4.4 standard. In the loader program size block, place the loader program size in the first 4 bytes, the loader program load address in 4 bytes at offset H’10, and the loader program destination address in 4 bytes at offset H’20.
Page 124 RZ/G3S Group 4. Boot Mode +H’04 +H’04 +H’00 Loader program data size (4 bytes) Loader program load address (4 bytes) Loader program Destination address (4 bytes) Don’t Care bytes +H’1FE +H’1FE H’55 H’AA Signature Figure 4.7 Structure of the Loader Program Size Block NOTE The loader program data size, loader program load address, and loader program destination address are expected to be stored in 4-byte little-endian.
Page 125 RZ/G3S Group 4. Boot Mode 4.2.2.5 Alternative Boot Operation Figure 4.8 shows the alternative boot operation to read the loader program. This boot program sets up the registers in SDHI channel 0 so that the SDHI operates with an 8-bit bus width when booting from the eMMC device. On the eMMC device side, the data bus width in the alternative boot operation is determined by the setting of the BOOT_BUS_WIDTH[177] field in the extended CSD register.
Page 126 RZ/G3S Group 4. Boot Mode (1) Partitions An eMMC device has multiple partitions (Figure 4.9). The partition used for booting can be specified in the PARTITION_CONFIG[179] field of the extended CSD (EXT_CSD) register. To boot up correctly, specify the boot partition in the extended CSD (EXT_CSD) register of the eMMC device as shown in Table 4.9 when writing a program to the eMMC device.
Page 127 RZ/G3S Group 4. Boot Mode 4.2.3 Boot Mode 2 (Serial Flash Memory (Single / Quad / Octal)) Table 4.10 shows the interface signals used for connection with the external device in boot mode 2 (1.8-V serial flash memory). Table 4.10 External Interface Signals Used in Boot Mode 2 Interface Module Pin Name...
Page 128 RZ/G3S Group 4. Boot Mode 4.2.3.1 External Connections Figure 4.10, Figure 4.11, and Figure 4.12 show the connections with the Single SPI memory and Quad SPI memory, respectively. This LSI XSPI_SPCLK SCLK XSPI_IO0 SI/SIO0 XSPI_IO1 SO/SIO1 XSPI_IO2 open XSPI_IO3 open XSPI_IO4 open XSPI_IO5...
Page 129 RZ/G3S Group 4. Boot Mode This LSI Quad SPI XSPI_SPCLK SCLK XSPI_IO0 SI/SIO0 XSPI_IO1 SO/SIO1 XSPI_IO2 SIO2 XSPI_IO3 SIO3 XSPI_IO4 open XSPI_IO5 open XSPI_IO6 open XSPI_IO7 open XSPI_DS open XSPI_CS0 XSPI_CS1 open XSPI_RESET# open XSPI_WP# open Terminals used during Boot Terminals not used during Boot Figure 4.11 Connections with Quad SPI Memory in Boot Mode 2...
Page 130 RZ/G3S Group 4. Boot Mode This LSI Octa SPI XSPI_SPCLK SCLK XSPI_IO0 SI/SIO0 XSPI_IO1 SO/SIO1 XSPI_IO2 SIO2 XSPI_IO3 SIO3 XSPI_IO4 SIO4 XSPI_IO5 SIO5 XSPI_IO6 SIO6 XSPI_IO7 SIO7 XSPI_DS XSPI_CS0 XSPI_CS1 open XSPI_RESET# open XSPI_WP# open Terminals used during Boot Terminals not used during Boot Figure 4.12 Connections Octa Memory in Boot Mode 2 R01UH1014EJ0110...
Page 131 RZ/G3S Group 4. Boot Mode 4.2.3.2 Overview of Operation This mode is used to boot this LSI from the user program stored in the Single or Quad flash memory device. The serial flash memory mounted in advance on the board is used in this mode. In this mode, the MD_BOOT2 pin is controlled by the voltage (1.8 V/3.3 V) of the target device.
Page 132 RZ/G3S Group 4. Boot Mode 4.2.3.4 Allocation of the Loader Program in the Serial Flash Memory Figure 4.13 shows the allocation of the loader program size block and loader program in the serial flash memory. Place the loader program size in the first 4 bytes, the load address in the next 4 bytes, and the destination address in the next 4 bytes.
Page 133 RZ/G3S Group 4. Boot Mode +H’04 +H’04 +H’00 Loader program data size (4 bytes) Loader program load address (4 bytes) Loader program Destination address (4 bytes) Don’t Care bytes +H’1FE +H’1FE H’55 H’AA Signature Figure 4.14 Structure of the Loader Program Size Block NOTE The loader program data size, loader program load address, and loader program destination address are expected to be stored in 4-byte little-endian.
Page 134 RZ/G3S Group 4. Boot Mode 4.2.4 Boot Mode 3 (SCIF Downloading) Table 4.11 shows the interface signals used for connection with the external device in boot mode 3 (SCIF downloading). Table 4.11 External Interface Signals Used in Boot Mode 3 Interface Module Pin Name Function...
Page 135 RZ/G3S Group 4. Boot Mode 4.2.4.2 Overview of Operation This mode is used to download the user program from the host PC. Upon detecting boot mode 3 according to the value read from the SYSC, the boot program makes the necessary settings of the SCIF0 module to access memory. The boot program handles the following steps to control the booting process.
Page 136 RZ/G3S Group 4. Boot Mode 4.2.4.3 Operation of Booting through SCIF Downloading SCIF download boot is launched from a loader program stored on an external PC via the FIFO built-in serial communication interface (SCIFA). The boot program executes the following processing. Set peripheral modules (SCIFA channel 0, GPIO) and set drive capability values.
Page 137 RZ/G3S Group 4. Boot Mode The data transmission and reception operation in SCIF communications (asynchronous) is shown in Figure 4.17. Idle state (mark state) (LSB) (MSB) Serial data Start Parity Transmit or receive data Stop bit 1 bit 7 or 8 bits 1 bit or 1 or 2 bits none...
Page 138 RZ/G3S Group 4. Boot Mode Loader Program Size Block The loader program size block defines information about where the loader program is stored and deployed. It has a fixed size of 512bytes and is stored in a fixed location for each boot device. The configuration of the loader program size block is shown in Figure 4.19, and the details of each field are shown in Table 4.12.
Page 139 RZ/G3S Group 4. Boot Mode Loader Program Storage This LSI On chip RAM Loader program data size H’000A_1E00 Loader program size block area Loadder Loader program load address program H’000A_2000 Loader Program size Expandable Area block Loader program Destination address Signature Loader program Loader program A...
Page 140 RZ/G3S Group 5. LSI Internal Bus LSI Internal Bus Overview 5.1.1 Features The bus system of this LSI provides a physical address space of 16 Gbytes (address bus width of 34 bits). The LSI internal bus of this LSI incorporates Arm CoreLink NIC-400, etc., and controls the following bus functions. Security control: Security attribute re-setting, Security level determination Address translation:...
Page 141 RZ/G3S Group 5. LSI Internal Bus 5.1.2 Block Diagram of LSI Internal Bus The LSI internal bus of this LSI consists of the ACPU bus, MCPU bus, and system bus. Figure 5.1 shows the configuration of the buses. ACPU bus: A bus connected to Cortex-A55, Cortex-M33_FPU, DDR memory controllers and Storage and Network MCPU bus: A bus connected to Cortex-M33 and serial interface units...
Page 142 RZ/G3S Group 5. LSI Internal Bus Cortex-A55 MPCore Core 0 32 Kbytes 32 Kbytes Crypto NEON (Option) Cortex-M33 Shared L3$ 256 Kbytes with FPU ACPU Bus DMA Controller Security DMAC (16 ch) RSIP Secure (Option) DMAC (16 ch) Cortex-M33 System TSU (1 ch) Internal Memory Internal Memory...
Page 143 RZ/G3S Group 5. LSI Internal Bus Area Maps 5.2.1 Overall Address Space Figure 5.2 shows the overall address space of this LSI and Table 5.1 shows the detailed address space. H’3_FFFF_FFFF Reserved area 11 Gbytes H’1_4000_0000 H’1_3FFF_FFFF H’1_0000_0000 DDR area 4 Gbytes H’0_4000_0000 H’0_3800_0000...
Page 144 RZ/G3S Group 5. LSI Internal Bus Table 5.1 Detailed Address Space (1/4) Start Address End Address Size Space Remarks H’1_4000_0000 H’3_FFFF_FFFF 11 Gbytes Reserved H’0_4000_0000 H’1_3FFF_FFFF 4 Gbytes DDR (Memory) H’0_3800_0000 H’0_3FFF_FFFF 128 Mbytes Reserved H’0_3000_0000 H’0_37FF_FFFF 128 Mbytes PCIe H’0_2000_0000 H’0_2FFF_FFFF 256 Mbytes...
Page 145 RZ/G3S Group 5. LSI Internal Bus Table 5.1 Detailed Address Space (2/4) Start Address End Address Size Space Remarks H’0_1183_0000 H’0_1183_FFFF 64 Kbytes Non-Secure DMAC (DMAC_NS) H’0_1182_0000 H’0_1182_FFFF 64 Kbytes Non-Secure DMAC (DMAC_NS) H’0_1181_0000 H’0_1181_FFFF 64 Kbytes Secure DMAC (DMAC_S) H’0_1180_0000 H’0_1180_FFFF 64 Kbytes...
Page 146 RZ/G3S Group 5. LSI Internal Bus Table 5.1 Detailed Address Space (3/4) Start Address End Address Size Space Remarks H’0_100A_C000 H’0_100A_FFFF 16 Kbytes Reserved H’0_100A_B400 H’0_100A_BFFF 3 Kbytes Reserved H’0_100A_B000 H’0_100A_B3FF 1 Kbyte RSPI ch4 H’0_100A_AC00 H’0_100A_AFFF 1 Kbyte RSPI ch3 H’0_100A_A800 H’0_100A_ABFF 1 Kbyte...
Page 147 RZ/G3S Group 5. LSI Internal Bus Table 5.1 Detailed Address Space (4/4) Start Address End Address Size Space Remarks H’0_1004_9400 H’0_1004_97FF 1 Kbyte POEGD H’0_1004_9000 H’0_1004_93FF 1 Kbyte POEGC H’0_1004_8C00 H’0_1004_8FFF 1 Kbyte POEGB H’0_1004_8800 H’0_1004_8BFF 1 Kbyte POEGA H’0_1004_8000 H’0_1004_87FF 2 Kbytes H’0_1004_0000...
Page 148 RZ/G3S Group 5. LSI Internal Bus 5.2.2 Cortex-M33/Cortex-M33_FPU Address Space Figure 5.3 shows the default memory map of Cortex-M33/Cortex-M33_FPU and an overview of the Cortex- M33/Cortex-M33_FPU address space for this LSI, and Table 5.2 shows the detailed address space. For the concept of the secure and non-secure states, see Section 3, System CPU Cortex-M33/Cortex-M33_FPU.
Page 149 RZ/G3S Group 5. LSI Internal Bus Table 5.2 Detailed Address Space of Cortex-M33/Cortex-M33_FPU (1/8) Start Address End Address Size Space Remarks H’E000_0000 H’FFFF_FFFF 512 Mbytes PPB / Vendor_SYS H’C000_0000 H’DFFF_FFFF 512 Mbytes Reserved H’B000_0000 H’BFFF_FFFF 256 Mbytes PCIe (Non-Secure) H’A000_0000 H’AFFF_FFFF 256 Mbytes PCIe (Secure)
Page 150 RZ/G3S Group 5. LSI Internal Bus Table 5.2 Detailed Address Space of Cortex-M33/Cortex-M33_FPU (2/8) Start Address End Address Size Space Remarks H’5187_0000 H’518F_FFFF 576 Kbytes Reserved H’5186_0000 H’5186_FFFF 64 Kbytes OTP (Non-Secure) H’5185_0000 H’5185_FFFF 64 Kbytes Reserved H’5184_0000 H’5184_FFFF 64 Kbytes Reserved Non-Secure DMAC (DMAC_NS) H’5183_0000...
Page 151 RZ/G3S Group 5. LSI Internal Bus Table 5.2 Detailed Address Space of Cortex-M33/Cortex-M33_FPU (3/8) Start Address End Address Size Space Remarks H’5041_0000 H’505F_FFFF 1984 Kbytes Reserved H’5040_0000 H’5040_FFFF 64 Kbytes MHU (Non-Secure) H’5030_0000 H’503F_FFFF 1 Mbyte Reserved H’5020_0000 H’502F_FFFF 1 Mbyte Reserved H’500E_0000 H’501F_FFFF...
Page 152 RZ/G3S Group 5. LSI Internal Bus Table 5.2 Detailed Address Space of Cortex-M33/Cortex-M33_FPU (4/8) Start Address End Address Size Space Remarks H’5004_C800 H’5004_CBFF 1 Kbyte SCIF ch4 (Non-Secure) H’5004_C400 H’5004_C7FF 1 Kbyte SCIF ch3 (Non-Secure) H’5004_C000 H’5004_C3FF 1 Kbyte SCIF ch2 (Non-Secure) H’5004_BC00 H’5004_BFFF 1 Kbyte...
Page 153 RZ/G3S Group 5. LSI Internal Bus Table 5.2 Detailed Address Space of Cortex-M33/Cortex-M33_FPU (5/8) Start Address End Address Size Space Remarks H’41C1_0000 H’41C1_FFFF 64 Kbytes SD ch1 (Secure) H’41C0_0000 H’41C0_FFFF 64 Kbytes SD ch0 (Secure) H’41B0_0000 H’41BF_FFFF 1 Mbyte Reserved H’41A0_0000 H’41AF_FFFF 1 Mbyte...
Page 154 RZ/G3S Group 5. LSI Internal Bus Table 5.2 Detailed Address Space of Cortex-M33/Cortex-M33_FPU (6/8) Start Address End Address Size Space Remarks H’4080_0000 H’40AF_FFFF 3 Mbytes Reserved H’4070_0000 H’407F_FFFF 1 Mbyte Reserved H’4060_0000 H’406F_FFFF 1 Mbyte Reserved H’4041_0000 H’405F_FFFF 1984 Kbytes Reserved H’4040_0000 H’4040_FFFF...
Page 155 RZ/G3S Group 5. LSI Internal Bus Table 5.2 Detailed Address Space of Cortex-M33/Cortex-M33_FPU (7/8) Start Address End Address Size Space Remarks H’4004_D800 H’4004_DFFF 2 Kbytes Reserved H’4004_D400 H’4004_D7FF 1 Kbyte SCI ch1 (Secure) H’4004_D000 H’4004_D3FF 1 Kbyte SCI ch0 (Secure) H’4004_CC00 H’4004_CFFF 1 Kbyte...
Page 156 RZ/G3S Group 5. LSI Internal Bus Table 5.2 Detailed Address Space of Cortex-M33/Cortex-M33_FPU (8/8) Start Address End Address Size Space Remarks H’0012_2000 H’0FFF_FFFF 260984 Kbytes Reserved H’0012_0000 H’0012_1FFF 8 Kbytes Reserved H’000E_0000 H’0011_FFFF 256 Kbytes SRAM ACPU1 (Memory) (Code, Secure) H’000A_0000 H’000D_FFFF 256 Kbytes...
Page 157 RZ/G3S Group 5. LSI Internal Bus Accessible Areas In the bus system of this LSI, each bus master unit can only access the areas that are used for register access or data transfer. Table 5.3 shows the areas that can be accessed from each master. The register area of TZC can be accessed only when Secure (AxPROT[1] = 0).
Page 158 RZ/G3S Group 5. LSI Internal Bus Table 5.3 Accessible Areas (2/2) Master Unit Slave Unit DMAC_NS × × × × ×       SDHI (ch0, ch1, ch2) × × × × ×     ...
Page 159 RZ/G3S Group 5. LSI Internal Bus Bus System Control 5.4.1 Security Control 5.4.1.1 Re-Setting the Security Attribute Output from Bus Masters This facility is for re-setting the security attributes of bus transactions that are by bus master units. Specifically, use the master access control register (SYS_MSTACCCTLn: n = 0, 1, 2, 6) to re-set the security attributes.
Page 160 RZ/G3S Group 5. LSI Internal Bus Table 5.4 List of Register Bits for Use in Re-setting of Security Attributes Write Access Control Bits* Read Access Control Bits* Bit for use in re-setting the security Bit for use in re-setting the security Bit for use in Bit for use in attributes immediately below...
Page 161 RZ/G3S Group 5. LSI Internal Bus 5.4.1.2 Determining the Security Levels of Bus Slaves This facility is for enabling or disabling access to a bus slave unit by comparing the security attribute that is input to the bus slave unit in a bus transaction with the security setting of the given slave. The security level can be set in one of the following ways.
Page 162 RZ/G3S Group 5. LSI Internal Bus Table 5.5 Security Levels Set by Using the Slave Control Register Security Attribute for Input Bus Transactions Non-privileged Privileged Non-privileged Privileged Setting of SL[1:0] Non-secure Non-secure Secure Secure Access allowed Access allowed Access allowed Access allowed Access not allowed Access allowed...
Page 163 RZ/G3S Group 5. LSI Internal Bus Table 5.7 Bus Slaves for which the Security Levels are Determined by Using the Slave Control Registers (2/3) Target Bus Slave for Control* Control Register* SL[1:0] Allocation Bits* GTM (channel 1) SYS_SLVACCCTL4 Bits [7:6] GTM (channel 2) SYS_SLVACCCTL4 Bits [9:8]...
Page 164 RZ/G3S Group 5. LSI Internal Bus Table 5.7 Bus Slaves for which the Security Levels are Determined by Using the Slave Control Registers (3/3) Target Bus Slave for Control* Control Register* SL[1:0] Allocation Bits* SCI (channel 1) SYS_SLVACCCTL8 Bits [15:14] SCI (channel 0) (IrDA) SYS_SLVACCCTL8 Bits [17:16]...
Page 165 RZ/G3S Group 5. LSI Internal Bus Table 5.8 Bus Slaves for which Security Levels are Determined by Using the Region ID Access Registers of the Target Bus Slave Security Control Unit for Control (locations of the control registers) Control Register* Control Bits* TZC (DDR) REGION_ID_ACCESS_<n>...
Page 166 RZ/G3S Group 5. LSI Internal Bus 5.4.2 Address Translation 5.4.2.1 34-Bit Address Space Access This LSI has bus master units that can handle up to a 34-bit address space and bus master units that can only handle up to a 32-bit address space (actual size of 4 Gbytes). This function enables a bus master unit that can only handle up to a 32-bit address space (actual size of 4 Gbytes) to access an address space of greater than 4 Gbytes.
Page 167 RZ/G3S Group 5. LSI Internal Bus 5.4.3 Bus Error Interrupt Generation This LSI generates a bus error interrupt when any of the following conditions is met. A bus error is generated when access is disabled by the security setting. ● A bus error is generated when access to a slave unit in the module stop state (MSTOP) is attempted.
Page 168 RZ/G3S Group 5. LSI Internal Bus 5.4.4 Address Map switching function 5.4.4.1 Address Remap Control This function switches the system address map using the selection signal SEL_SPI_OCTA controlled by the SYS_IPCONT_SEL_SPI_OCTA register of the system control register (SYS Reg). The address map switching target is the Mem/Write Buf/Reg area of xSPI and the Mem/Reg area of Octa Flash/RAM.
Page 169 RZ/G3S Group 5. LSI Internal Bus 5.4.4.2 MSTOP Control Function Module stop control is performed for each of the xSPI and Octa Flash/RAM areas for address map switching using one MSTOP control signal (MSTOP_MHSPI, MSTOP_MXOCTA). For module stop control, see Section 5.4.1.2, Determining the Security Levels of Bus Slaves.
Page 170 RZ/G3S Group 6. System Controller (SYSC) System Controller (SYSC) Overview 6.1.1 Features SYSC is a unit that performs system control of this LSI and has the following functions. Product information, external terminal state capture function ● − Management of product information of this LSI, and external terminal status Security control function ●...
Page 171 RZ/G3S Group 6. System Controller (SYSC) 6.1.2 Block Diagram of SYSC The block diagram of SYSC is shown in Figure 6.1. System Controller (SYSC) Security control Bus modules Bus modules Address translation table APB4 bus Internal register access control Each IP APB I/F CoreSight Arbitration...
Page 172 RZ/G3S Group 6. System Controller (SYSC) Register Configuration Table 6.1 shows the register configuration of SYSC. The address of the SYSC register is represented by the offset address from the base address. SYSC base address is as follows: SYSC base address: H’0_1102_0000 (Overall Address Space) SYSC base address: H’5102_0000 (Cortex-M33 Address Space Non-Secure) SYSC base address: H’4102_0000 (Cortex-M33 Address Space Secure) Base address of Non-Secure and Secure are exchangeable by SYS_IPCONT_IDAUZERONS register for...
Page 173 RZ/G3S Group 6. System Controller (SYSC) Table 6.1 SYSC Register Configuration (2/3) Offset Access Register Name Abbreviation Initial Value Address Size WDT2 Control Register SYS_WDT2_CTRL H’0001_0000 H’0270 DDR MCREG control Register SYS_DDR_MCAR_CTRL H’0000_0000 H’0304 XSPI Start Address for slave0 Register SYS_XSPI_MAP_STAADD_C H’2000_0000 H’0348...
Page 174 RZ/G3S Group 6. System Controller (SYSC) Table 6.1 SYSC Register Configuration (3/3) Offset Access Register Name Abbreviation Initial Value Address Size Lowpower Sequence Control Register5 SYS_LP_CTL5 H’0000_0000 H’0D14 Lowpower Sequence Control Register6 SYS_LP_CTL6 H’0000_0000 H’0D18 Lowpower Sequence Control Register7 SYS_LP_CTL7 H’0000_0000 H’0D1C Lowpower Sequence CM33 Control Register0 SYS_LP_CM33CTL0...
Page 175 RZ/G3S Group 6. System Controller (SYSC) Register Descriptions 6.3.1 Master Access Control Register 0 (SYS_MSTACCCTL0) This register sets the secure attribute and privilege attribute of transactions from DMAC. — — — — — — — — — — — — —...
Page 176 RZ/G3S Group 6. System Controller (SYSC) Initial Bit Name Value Description DMAC1_AW Non-Secure DMAC write access secure attribute 1:Non- Secure The value of this bit is always 1. The written value is ignored. DMAC1_AWP Non-Secure DMAC write access privilege attribute 0: Non-privileged access The value of this bit is always 0.
Page 177 RZ/G3S Group 6. System Controller (SYSC) 6.3.2 Master Access Control Register 1 (SYS_MSTACCCTL1) This register sets the secure attribute and privilege attribute of transactions from GbEthernet and SDHI/eMMC. GEther1 GEther0 GEther1 GEther1 GEther1 GEther1 GEther1 GEther0 GEther0 GEther0 GEther0 GEther0 —...
Page 178 RZ/G3S Group 6. System Controller (SYSC) Initial Bit Name Value Description GEther0_AW GbEthernet (channel 0) write access security attribute source selection* 0: AWPROT[1:0] is always 10b 1: GEther0_AWPU is selected for AWPROT [0], and GEther0_AWNS is selected for AWPROT [1]. —...
Page 179 RZ/G3S Group 6. System Controller (SYSC) Initial Bit Name Value Description — Reserved Whenever it is read, 0 is read. The written value will be ignored. SDHI0_AWN SDHI/eMMC (channel 0) write access secure attribute* 0: Secure 1: Non-secure SDHI0_AWP SDHI/eMMC (channel 0) write access privilege attribute* 0: Non-privileged access 1: Privileged access Note 1.
Page 180 RZ/G3S Group 6. System Controller (SYSC) 6.3.3 Master Access Control Register 2 (SYS_MSTACCCTL2) This register sets the secure attribute and privilege attribute of transactions from USB2.0. USB2_1 USB2_1 USB2_1 USB2_1 USB2_1 USB2_1 — — — — — — — — H_ARS —...
Page 181 RZ/G3S Group 6. System Controller (SYSC) Initial Bit Name Value Description USB2_0D_A USB2.0 (channel 0, function) read access secure attribute* 0: Secure 1: Non-secure USB2_0D_A USB2.0 (channel 0, function) read access privilege attribute* 0: Non-privileged access 1: Privileged access USB2_0D_A USB2.0 (channel 0, function) write access security attribute source selection* WSEL 0: AWPROT[0] selects the HPROT[1] value from USB2.0 channel 0, Function, and...
Page 182 RZ/G3S Group 6. System Controller (SYSC) 6.3.4 Master Access Control Register 6 (SYS_MSTACCCTL6) This register sets the secure attribute and privilege attribute of transactions from SDHI ch2 and PCIe. — — — — — — — — — — — —...
Page 183 RZ/G3S Group 6. System Controller (SYSC) Initial Bit Name Value Description SDHI2_ARPU 0 SDHI (channel 2) read access privilege attribute* 0: Non-privileged access 1: Privileged access SDHI2_AWS SDHI (channel 2) write access security attribute source selection* 0: AWPROT[1:0] is always 10b 1: SDHI2_AWPU is selected for AWPROT[0], and SDHI2_AWNS is selected for AWPROT[1].
Page 184 RZ/G3S Group 6. System Controller (SYSC) 6.3.5 Slave Access Control Register 0 (SYS_SLVACCCTL0) This register sets the security levels for determining whether to enable or disable access to each set of registers in the SRAM ACPU0 (Reg), SRAM_ACPU1 (Reg), SRAM_MCPU0 (Reg) and SRAM MCPU1 (Reg). —...
Page 185 RZ/G3S Group 6. System Controller (SYSC) 6.3.6 Slave Access Control Register 2 (SYS_SLVACCCTL2) This register sets the security levels for determining whether to enable or disable access to each set of registers in the TZC. — — — — — —...
Page 186 RZ/G3S Group 6. System Controller (SYSC) 6.3.7 Slave Access Control Register 3 (SYS_SLVACCCTL3) This register sets the security levels for determining whether to enable or disable access to each set of registers in the MHU, GPIO, IA55/IM33, GIC, SYC, SYSC, CPG and CoreSight. —...
Page 187 RZ/G3S Group 6. System Controller (SYSC) 6.3.8 Slave Access Control Register 4 (SYS_SLVACCCTL4) This register sets the security levels for determining whether to enable or disable access to each set of registers in the DMAC, GTM, WDT and RTC. — —...
Page 188 RZ/G3S Group 6. System Controller (SYSC) 6.3.9 Slave Access Control Register 5 (SYS_SLVACCCTL5) This register sets the security levels for determining whether to enable or disable access to each set of registers in the MTU3a, POE3, GPT, POEG, DDR <Reg>, xSPI <Reg> and Octa Flash/RAM <Reg>. —...
Page 189 RZ/G3S Group 6. System Controller (SYSC) 6.3.10 Slave Access Control Register 6 (SYS_SLVACCCTL6) This register sets the security levels for determining whether to enable or disable access to each set of registers in the USB2.0, SDHI/eMMC, GbEthernet and PCIe. — —...
Page 190 RZ/G3S Group 6. System Controller (SYSC) 6.3.11 Slave Access Control Register 7 (SYS_SLVACCCTL7) This register sets the security levels for determining whether to enable or disable access to each set of registers in the I2C, I3C, CANFD and RSPI. — —...
Page 191 RZ/G3S Group 6. System Controller (SYSC) 6.3.12 Slave Access Control Register 8 (SYS_SLVACCCTL8) This register sets the security levels for determining whether to enable or disable access to each set of registers in the SCIF, SCI and IrDA. — — —...
Page 192 RZ/G3S Group 6. System Controller (SYSC) 6.3.13 Slave Access Control Register 9 (SYS_SLVACCCTL9) This register sets the security levels for determining whether to enable or disable access to each set of registers in the SSIF, SRC, SPDIF and PDM. — —...
Page 193 RZ/G3S Group 6. System Controller (SYSC) 6.3.14 Slave Access Control Register 10 (SYS_SLVACCCTL10) This register sets the security levels for determining whether to enable or disable access to each set of registers in the ADC and TSU. — — — —...
Page 194 RZ/G3S Group 6. System Controller (SYSC) 6.3.15 Slave Access Control Register 11 (SYS_SLVACCCTL11) This register sets the security levels for determining whether to enable or disable access to each set of registers in the OTP and VBATT. — — — —...
Page 195 RZ/G3S Group 6. System Controller (SYSC) 6.3.16 Slave Access Control Register 12 (SYS_SLVACCCTL12) This register sets the security levels for determining whether to enable or disable access to each set of registers in the Cortex-A55 control register and Cortex-M33/Cortex-M33_FPU control register in SYSC. —...
Page 196 RZ/G3S Group 6. System Controller (SYSC) 6.3.18 Slave Access Control Register 16 (SYS_SLVACCCTL16) This register sets the security levels for determining whether to enable or disable access to each set of registers in the AOF control register in SYSC. — —...
Page 197 RZ/G3S Group 6. System Controller (SYSC) 6.3.20 Slave Access Control Register 18 (SYS_SLVACCCTL18) This register sets the security levels for determining whether to enable or disable access to each set of registers in the general purpose register in SYSC. — —...
Page 198 RZ/G3S Group 6. System Controller (SYSC) 6.3.22 ECCRAM0 ECC Setting Register (SYS_RAM0_ECC) This register is a register that enables and disables the ECC function of ECCRAM0 (SRAM ACPU0). — — — — — — — — — — — — —...
Page 199 RZ/G3S Group 6. System Controller (SYSC) 6.3.24 ECCRAM1 ECC Setting Register (SYS_RAM1_ECC) This register is a register that enables and disables the ECC function of ECCRAM1 (SRAM ACPU1). — — — — — — — — — — — — —...
Page 200 RZ/G3S Group 6. System Controller (SYSC) 6.3.26 ECCRAM2 ECC Setting Register (SYS_RAM2_ECC) This register is a register that enables and disables the ECC function of ECCRAM2 (SRAM MCPU0). — — — — — — — — — — — — —...
Page 201 RZ/G3S Group 6. System Controller (SYSC) 6.3.28 ECCRAM3 ECC Setting Register (SYS_RAM3_ECC) This register is a register that enables and disables the ECC function of ECCRAM3 (SRAM MCPU1). — — — — — — — — — — — — —...
Page 202 RZ/G3S Group 6. System Controller (SYSC) 6.3.30 WDT0 Control Register (SYS_WDT0_CTRL) This register is the register that set the count control of WDT0. WDTST — — — — — — — — — — — — — — — OPMAS Initial Value WDTST —...
Page 203 RZ/G3S Group 6. System Controller (SYSC) 6.3.31 WDT1 Control Register (SYS_WDT1_CTRL) This register is the register that set the count control of WDT1. WDTST — — — — — — — — — — — — — — — OPMAS Initial Value WDTST —...
Page 204 RZ/G3S Group 6. System Controller (SYSC) 6.3.32 WDT2 Control Register (SYS_WDT2_CTRL) This register is the register that set the count control of WDT2. WDTST — — — — — — — — — — — — — — — OPMAS Initial Value WDTST —...
Page 205 RZ/G3S Group 6. System Controller (SYSC) 6.3.33 DDR Retention Mode Control Register (SYS_DDR_MCAR_CTRL) This register is the register that control retention mode of DDR. MCAR_ — — — — — — — — — — — — — — — CTRL Initial Value —...
Page 206 RZ/G3S Group 6. System Controller (SYSC) 6.3.34 XSPI CS0 Start Address Register (SYS XSPI_MAP_STAADD_CS0) This register is the register that indicates the start address of xSPI CS0. MAP_STAADD_CS0 Initial Value MAP_STAADD_CS0 Initial Value Initial Bit Name Value Description 31 to 0 MAP_STAAD H’2000_0 Start Address for xSPI CS0...
Page 207 RZ/G3S Group 6. System Controller (SYSC) 6.3.36 XSPI CS1 Start Address Register (SYS XSPI_MAP_STAADD_CS1) This register is the register that indicates the start address of xSPI CS1. MAP_STAADD_CS1 Initial Value MAP_STAADD_CS1 Initial Value Initial Bit Name Value Description 31 to 0 MAP_STAAD All 0 Start Address for xSPI CS1...
Page 208 RZ/G3S Group 6. System Controller (SYSC) 6.3.38 GEther0 Config Register (SYS_GETH0_CFG) This register is the register that indicates the state of Ether ch0. FEC_GI — — — — — — — GA_EN — — — — — — — — ABLE Initial Value —...
Page 209 RZ/G3S Group 6. System Controller (SYSC) 6.3.39 Gether1 Config Register (SYS_GETH1_CFG) This register is the register that indicates the state of Ether ch1. FEC_GI — — — — — — — GA_EN — — — — — — — — ABLE Initial Value —...
Page 210 RZ/G3S Group 6. System Controller (SYSC) 6.3.40 PCIe Config Register (SYS_PCIE_CFG) This register is the register that set configuration of PCIe. — — — — — — — — — — — — — — — — Initial Value ALLOW —...
Page 211 RZ/G3S Group 6. System Controller (SYSC) 6.3.41 PCIe Monitor Register (SYS_PCIE_MON) This register is a register that shows PCIe power, clock and device status. — — — — — — — — — — — — — — — — Initial Value PMU_P D_STATE_OUT_...
Page 212 RZ/G3S Group 6. System Controller (SYSC) 6.3.42 PCIe Error Monitor Register (SYS_PCIE_ERR_MON) This register is a register that shows PCIe error detection results. — — — — — — — — — — — — — — — — Initial Value ERR_N ERR_F ERR_C...
Page 213 RZ/G3S Group 6. System Controller (SYSC) 6.3.43 PCIe PHY Register (SYS_PCIE_PHY) This register is a register that set the receiver termination setting of PCIe. — — — — — — — — — — — — — — — — Initial Value MODE_ RXTER...
Page 214 RZ/G3S Group 6. System Controller (SYSC) 6.3.44 I2C0 Config Register (SYS_I2C0_CFG) This register is a register that set the bypass mode of the analog filter of I2C ch0. — — — — — — — — — — — — —...
Page 215 RZ/G3S Group 6. System Controller (SYSC) 6.3.46 I2C2 Config Register (SYS_I2C2_CFG) This register is a register that set the bypass mode of the analog filter of I2C ch2. — — — — — — — — — — — — —...
Page 216 RZ/G3S Group 6. System Controller (SYSC) 6.3.48 I3C Config Register (SYS_I3C_CFG) This register is a register that set the bypass mode of the analog filter of I3C. — — — — — — — — — — — — — —...
Page 217 RZ/G3S Group 6. System Controller (SYSC) 6.3.50 CA55 Core0 Reset Vector Address High Configuration Register (SYS_CA55_CFG_RVAH0) This register is a register that set the reset vector address of Cortex-A55 core0. — — — — — — — — — — —...
Page 218 RZ/G3S Group 6. System Controller (SYSC) 6.3.52 CM33 Config Register1 (SYS_CM33_CFG1) This register is the register that set cortex-M33 non-secure Systick. — — — — — — CONFIGNSSYSTICK[25:0] Initial Value CONFIGNSSYSTICK[25:0] Initial Value Initial Bit Name Value Description 31 to 26 —...
Page 219 RZ/G3S Group 6. System Controller (SYSC) 6.3.54 CM33 Config Register3 (SYS_CM33_CFG3) This register is the register that set the non-secure vector address of Cortex-M33. INITNSVTOR[31:7] Initial Value INITNSVTOR[31:7] — — — — — — — Initial Value Initial Bit Name Value Description 31 to 7...
Page 220 RZ/G3S Group 6. System Controller (SYSC) 6.3.56 CM33_FPU Config Register0 (SYS_CM33FPU_CFG0) This register is the register that set the secure Systick of Cortex-M33_FPU. — — — — — — CONFIGSSYSTICK[25:0] Initial Value CONFIGSSYSTICK[25:0] Initial Value Initial Bit Name Value Description 31 to 26 —...
Page 221 RZ/G3S Group 6. System Controller (SYSC) 6.3.58 CM33_FPU Config Register2 (SYS_CM33FPU_CFG2) This register is the register that set the secure vector address of Cortex-M33_FPU. INITSVTOR[31:7] Initial Value INITSVTOR[31:7] — — — — — — — Initial Value Initial Bit Name Value Description 31 to 7...
Page 222 RZ/G3S Group 6. System Controller (SYSC) 6.3.60 CM33_FPU Lock Register (SYS_CM33FPU_LOCK) This register is a register that set the vector-address change permission of Cortex-M33_FPU. — — — — — — — — — — — — — — — — Initial Value LOCKS LOCKN...
Page 223 RZ/G3S Group 6. System Controller (SYSC) 6.3.61 LSI Mode Signal Register (SYS_LSI_MODE) This register indicates the state of the BOOTSELCPU terminal, the MD_BOOT terminal, the DEBUGEN terminal, the MD_CLKS terminal, and the MD_BYPASS terminal. STAT_S — — — — — —...
Page 224 RZ/G3S Group 6. System Controller (SYSC) 6.3.62 LSI Device ID Register (SYS_DEVID) This register indicates the product specific device ID. DEV_ID[31:28] DEV_ID[27:0] Initial Value — — — — DEV_ID[27:0] Initial Value Initial Bit Name Value Description 31 to 28 DEV_ID —...
Page 225 RZ/G3S Group 6. System Controller (SYSC) 6.3.63 LSI Product Register (SYS_LSI_PRR) This register indicates information about product options. — — — — — — — — — — — — — — — — Initial Value — — — — —...
Page 226 RZ/G3S Group 6. System Controller (SYSC) 6.3.64 SYS_AOF0 This register is an address offset register for accessing the 34-bit address space from SD ch0/ch1. OFS11_SXSDHI_1 OFS10_SXSDHI_1 OFS01_SXSDHI_1 OFS00_SXSDHI_1 Initial Value OFS11_SXSDHI_0 OFS10_SXSDHI_0 OFS01_SXSDHI_0 OFS00_SXSDHI_0 Initial Value Initial Bit Name Value Description 31 to 28 OFS11_SXS...
Page 227 RZ/G3S Group 6. System Controller (SYSC) 6.3.65 SYS_AOF1 This register is an address offset register for accessing the 34-bit address space from Ether ch0/ch1. OFS11_SXGIGE_1 OFS10_SXGIGE_1 OFS01_SXGIGE_1 OFS00_SXGIGE_1 Initial Value OFS11_SXGIGE_0 OFS10_SXGIGE_0 OFS01_SXGIGE_0 OFS00_SXGIGE_0 Initial Value Initial Bit Name Value Description 31 to 28 OFS11_SXGI...
Page 228 RZ/G3S Group 6. System Controller (SYSC) 6.3.66 SYS_AOF2 This register is an address offset register for accessing the 34-bit address space from USB2.0 ch0/ch1 Host. OFS11_SXUSB2_1 OFS10_SXUSB2_1 OFS01_SXUSB2_1 OFS00_SXUSB2_1 Initial Value OFS11_SXUSB2_0_H OFS10_SXUSB2_0_H OFS01_SXUSB2_0_H OFS00_SXUSB2_0_H Initial Value Initial Bit Name Value Description 31 to 28...
Page 229 RZ/G3S Group 6. System Controller (SYSC) 6.3.67 SYS_AOF3 This register is an address offset register for accessing the 34-bit address space from USB2.0 ch0 Function. — — — — — — — — — — — — — — — —...
Page 230 RZ/G3S Group 6. System Controller (SYSC) 6.3.68 SYS_AOF6 This register is an address offset register for accessing the 34-bit address space from Secure/Non-Secure DMAC. OFS11_SXDMAC_NS OFS10_SXDMAC_NS OFS01_SXDMAC_NS OFS00_SXDMAC_NS Initial Value OFS11_SXDMAC_S OFS10_SXDMAC_S OFS01_SXDMAC_S OFS00_SXDMAC_S Initial Value Initial Bit Name Value Description 31 to 28 OFS11_SXD...
Page 231 RZ/G3S Group 6. System Controller (SYSC) 6.3.69 SYS_AOF9 This register is an address offset register for accessing the 34-bit address space from SDHI ch2. — — — — — — — — — — — — — — — — Initial Value OFS11_SXSDHI_2 OFS10_SXSDHI_2...
Page 232 RZ/G3S Group 6. System Controller (SYSC) 6.3.70 SYS_LP_CTL1 This register is a register that requests the transition to low power consumption mode and confirms the status. CM33F CM33S CA55SL PUSLE — — LEEP_A — — — EEP_A — — — —...
Page 233 RZ/G3S Group 6. System Controller (SYSC) Initial Bit Name Value Description — Reserved When read, the initial value is read. When writing, be sure to write the initial value. Operation is not guaranteed if a value other than the initial value is written. CA55SLEEP_ Cortex-A55 Sleep Mode transition request 0: There is no transition request to Cortex-A55 Sleep Mode...
Page 234 RZ/G3S Group 6. System Controller (SYSC) 6.3.71 SYS_LP_CTL2 This register is set before and after Cortex-A55 Sleep Mode. — — — — — — — — — — — — — — — — Initial Value CA55_S — — — —...
Page 235 RZ/G3S Group 6. System Controller (SYSC) 6.3.72 SYS_LP_CTL5 This register controls the low power mode. — — — — — — — — — — — — — — — — Initial Value CM33F AMCLK ASCLK CM33S CA55SL — — —...
Page 236 RZ/G3S Group 6. System Controller (SYSC) Initial Bit Name Value Description ASCLKQDEN Cortex-A55 ACE Asynchronous Bridge Slave Interface QDENY Factor ASCLKQDENY Flag 0: No Deny response (clear with 0 write) 1: Deny response (SYS_CA55_DENY interrupt occurs) — Reserved When read, the initial value is read. When writing, be sure to write the initial value. Operation is not guaranteed if a value other than the initial value is written.
Page 237 RZ/G3S Group 6. System Controller (SYSC) 6.3.73 SYS_LP_CTL6 This register controls the low power mode. — — — — — — — — — — — — — — — — Initial Value CM33F AMCLK ASCLK CM33S CA55SL — — —...
Page 238 RZ/G3S Group 6. System Controller (SYSC) Initial Bit Name Value Description ASCLKQDEN Cortex-A55 ACE Asynchronous Bridge Slave Interface QDENY Configuration Factor Mask 0: Masks the configuration factors ASCLKQDENY_F for cortex-A55 ACE asynchronous bridge slave interface QDENY 1: Do not mask the configuration factor ASCLKQDENY_F for Cortex-A55 ACE Asynchronous bridge slave Interface QDENY —...
Page 239 RZ/G3S Group 6. System Controller (SYSC) 6.3.74 SYS_LP_CTL7 This register controls the low power mode. — — — — — — — — — — — — — — — — Initial Value IM33FP IM33_M — — — — — —...
Page 240 RZ/G3S Group 6. System Controller (SYSC) 6.3.75 SYS_LP_CM33CTL0 This register controls the low power mode of Cortex-M33. — — — — — — — — — — — — — — — — Initial Value — — — SYSRE SLEEP SLEEP —...
Page 241 RZ/G3S Group 6. System Controller (SYSC) 6.3.76 SYS_LP_CA55CK_CTL1 This register controls the low power mode of Cortex-A55. — — — — — — — — — — — — — — — — Initial Value PDBGC GICCLK ATCLK AMCLK ASCLK PCLKQ —...
Page 242 RZ/G3S Group 6. System Controller (SYSC) 6.3.77 SYS_LP_CA55CK_CTL2 This register controls the low power mode of Cortex-A55. — — — — — — — — — — — — — — — — Initial Value PDBGC GICCLK ATCLK PCLKQ AMCLK ASCLK —...
Page 243 RZ/G3S Group 6. System Controller (SYSC) Initial Bit Name Value Description ASCLKQREQ Set the level of the QREQn signal to the ACE asynchronous bridge Slave Interface on cortex-A55. When this register is read, the value set at the time of the write is read. This register represents the state of the Q-channel in combination with ASCLKQACCEPTn and ASCLKQDENY.
Page 244 RZ/G3S Group 6. System Controller (SYSC) 6.3.78 SYS_LP_CA55CK_CTL3 This register controls the low power mode of Cortex-A55. PDBGC GICCLK ATCLK PCLKQ AMCLK ASCLK — — — — LKQDE — — — — — — QDENY QDENY DENY QDENY QDENY Initial Value —...
Page 245 RZ/G3S Group 6. System Controller (SYSC) Initial Bit Name Value Description ASCLKQDEN — Represents the status of the QDENY signal from the ACE asynchronous bridge Slave Interface on cortex-A55. This register represents the state of the Q-channel in combination with ASCLKQREQn and ASCLKQACCEPTn.
Page 246 RZ/G3S Group 6. System Controller (SYSC) 6.3.79 SYS_LP_CM33FPUCTL0 This register controls the low power mode of Cortex-M33_FPU. — — — — — — — — — — — — — — — — Initial Value — — — SYSRE SLEEP SLEEP —...
Page 247 RZ/G3S Group 6. System Controller (SYSC) 6.3.80 Isolation Cell Control Register (SYS_PD_ISO_CTRL) This register is isolation cell in the PD_ISOVCC region control register. — — — — — — — — — — — — — — — — Initial Value PD_ISO —...
Page 248 RZ/G3S Group 6. System Controller (SYSC) 6.3.81 DDRPHY Control Register (PWRDN_DDRPHY_CTRL) This register is DDR PHY control register. — — — — — — — — — — — — — — — — Initial Value DDRPH DDRPJ DDRPH DDRPH DDRPH DDRPH —...
Page 249 RZ/G3S Group 6. System Controller (SYSC) 6.3.82 Isolation Region IO Buffer SE18 Control Register (ISO_IOBUF_SE18_CTRL) This register is SE18 of IO buffer in the isolation region control register. — — — — — — — — — — — — —...
Page 250 RZ/G3S Group 6. System Controller (SYSC) 6.3.84 PCIe RST_RSM_B Terminal Control Register (SYS_PCIE_RST_RSM_B) This register is RST_RSM_B terminal of PCIe control register. — — — — — — — — — — — — — — — — Initial Value PCIE_R —...
Page 251 RZ/G3S Group 6. System Controller (SYSC) 6.3.86 General Register1 (SYS_GPREG_1) This register is a general-purpose register. GPREG1[31:0] Initial Value GPREG1[31:0] Initial Value Initial Bit Name Value Description 31 to 0 GPREG1 H’0000_0 General-purpose register 1 [31:0] It is a 32-bit register. It is possible to write any value, read the written value.
Page 252 RZ/G3S Group 6. System Controller (SYSC) 6.3.88 General Register3 (SYS_GPREG_3) This register is a general-purpose register. GPREG3[31:0] Initial Value GPREG3[31:0] Initial Value Initial Bit Name Value Description 31 to 0 GPREG3 H’0000_0 General-purpose register 3 [31:0] It is a 32-bit register. It is possible to write any value, read the written value.
Page 253 RZ/G3S Group 6. System Controller (SYSC) 6.3.90 Cortex-M33 Address Space Definition Register (SYS_IPCONT_ IDAUZERONS) This register is Cortex-M33 Address Space definition register. — — — — — — — — — — — — — — — — Initial Value IDAUZE —...
Page 254 RZ/G3S Group 6. System Controller (SYSC) Operation 6.4.1 External Terminal State Capture Function Captures the state of the following five external terminals at the rising edge of PRST# terminal and holds them into the SYS_LSI_MODE register. The value is not updated by a reset that occurs inside the LSI. BOOTCPUSEL ●...
Page 255 RZ/G3S Group 7. Clock Pulse Generator (CPG) Clock Pulse Generator (CPG) This chapter describes the functions of the clock pulse generator module (CPG). Features 7.1.1 Overview Table 7.1 provides a list of CPG features. Table 7.1 List of Functions Features Specification ●...
Page 256 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.1.2 CPG Configuration Figure 7.1 shows the CPG configuration. CPG_CTL SYSC Low Power Cortex-A55 Control Cortex-M33 Cortex-M33 (FPU) Clock Control CPG_CGC Clock Generate Clock Clock PLL1 Selector PLL2 Unit PLL3 • • PLL4 •...
Page 257 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.1.3 Pin Description The table below shows a list of CPG pins. Table 7.2 Pin List Name Pin Name Functions Mode control pin MD_BOOT0 Set the operating mode. Do not change during PRST# pin asserts and after negating until the MD_BOOT1 operating mode is confirmed.
Page 258 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.1.4 Clock 7.1.4.1 Clock System Diagram Figure 7.2 and Figure 7.3 show the clock system diagram. DIV_PLL1 PLL1 1/1,1/2,1/4,1/8 Iϕ 1100 MHz 24 MHz CPG_PL1_DDIV[1:0] DIV_PLL2_100 PLL2 1/1,1/2,1/4,1/8,1/32 P0ϕ 1600 MHz CPG_PL2_DDIV[6:4] P4ϕ P5ϕ...
Page 259 RZ/G3S Group 7. Clock Pulse Generator (CPG) A’ PLL3 M0ϕ 1600 MHz DIV_PLL3_200 1/1,1/2,1/4,1/8,1/32 P1ϕ CPG_PL3_DDIV[2:0] DIV_PLL3_100 1/1,1/2,1/4,1/8,1/32 P2ϕ CPG_PL3_DDIV[6:4] DIV_PLL3_200MCPU 1/1,1/2,1/4,1/8,1/32 P3ϕ CPG_PL3_DDIV[10:8] ATϕ ZTϕ SEL_OCTA CPG_OCTA_SSEL[1:0] DIV_OCTA CPG_OCTA_DDIV[1:0] 1/1,1/2,1/4,1/8,1/32 OC0ϕ OC1ϕ SEL_SPI CPG_SPI_SSEL[1:0] DIV_SPI CPG_SPI_DDIV[1:0] 1/1,1/2,1/4,1/8,1/32 SPI0ϕ SPI1ϕ B’...
Page 260 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.1.4.2 Clock List Please refer to another file for the clock list. R01UH1014EJ0110 Rev.1.10 Page 260 of 3776 Nov 30, 2023...
Page 261 RZ/G3S Group 7. Clock Pulse Generator (CPG) Register Description 7.2.1 Register Attributes The following table shows the register attributes described in Register Details. Table 7.3 Register Attributes Register Attributes Description A register that can be read and written. A register that can read and 0b write. 1b Write is invalid. A register that can read and 1b write.
Page 262 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.2 Register Classification The table below shows the general classification of the register space in this module. The address of the CPG register is represented by an offset address from the CPG-based address. Base Address: H’0_1101_0000 (Cortex-A55 Address Space) Base Address: H’4101_0000 (Cortex-M33/Cortex-M33_FPU Address Space Secure) Base Address: H’5101_0000 (Cortex-M33/Cortex-M33_FPU Address Space Non-Secure )
Page 263 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.3 Register Configuration Table 7.5 Register List (1/7) Access Register Name Abbreviation Initial Value* Address* Size PLL1 (SSCG) Standby Control Register CPG_PLL1_STBY H’0000_0005 H’000 PLL4 (SSCG) Standby Control Register CPG_PLL4_STBY H’0000_0004 H’030 PLL6 (SSCG) Standby Control Register CPG_PLL6_STBY H’0000_0001 H’050...
Page 264 RZ/G3S Group 7. Clock Pulse Generator (CPG) Table 7.5 Register List (2/7) Access Register Name Abbreviation Initial Value* Address* Size Clock Control Register GTM CPG_CLKON_GTM H’0000_0000 H’534 Clock Control Register MTU CPG_CLKON_MTU H’0000_0000 H’538 Clock Control Register POE3 CPG_CLKON_POE3 H’0000_0000 H’53C Clock Control Register GPT CPG_CLKON_GPT...
Page 265 RZ/G3S Group 7. Clock Pulse Generator (CPG) Table 7.5 Register List (3/7) Access Register Name Abbreviation Initial Value* Address* Size Clock Monitor Register SRAM_MCPU CPG_CLKMON_SRAM_MCP H’0000_0003 H’68C Clock Monitor Register GIC600 CPG_CLKMON_GIC600 H’0000_0001 H’694 Clock Monitor Register IA55 CPG_CLKMON_IA55 H’0000_0003 H’698 Clock Monitor Register IM33 CPG_CLKMON_IM33...
Page 266 RZ/G3S Group 7. Clock Pulse Generator (CPG) Table 7.5 Register List (4/7) Access Register Name Abbreviation Initial Value* Address* Size Clock Monitor Register OTFDE_DDR CPG_CLKMON_OTFDE_DD H’0000_0000 H’778 Clock Monitor Register OTFDE_SPI CPG_CLKMON_OTFDE_SPI H’0000_0000 H’780 Clock Monitor Register PDM CPG_CLKMON_PDM H’0000_0000 H’784 Clock Monitor Register PCI CPG_CLKMON_PCI...
Page 267 RZ/G3S Group 7. Clock Pulse Generator (CPG) Table 7.5 Register List (5/7) Access Register Name Abbreviation Initial Value* Address* Size Reset Control Register REG0_BUS CPG_RST_REG0_BUS H’0000_0001 H’8CC Reset Control Register PERI_CPU CPG_RST_PERI_CPU H’0000_0003 H’8D0 Reset Control Register PERI_DDR CPG_RST_PERI_DDR H’0000_0001 H’8D8 Reset Control Register AXI_TZCDDR CPG_RST_AXI_TZCDDR...
Page 268 RZ/G3S Group 7. Clock Pulse Generator (CPG) Table 7.5 Register List (6/7) Access Register Name Abbreviation Initial Value* Address* Size Reset Monitor Register TSU CPG_RSTMON_TSU H’0000_0003 H’A2C Reset Monitor Register AXI_ACPU_BUS CPG_RSTMON_AXI_ACPU_ H’0000_0000 H’A34 Reset Monitor Register AXI_MCPU_BUS CPG_RSTMON_AXI_MCPU_ H’0000_0000 H’A38 Reset Monitor Register AXI_COM_BUS CPG_RSTMON_AXI_COM_B...
Page 269 RZ/G3S Group 7. Clock Pulse Generator (CPG) Table 7.5 Register List (7/7) Access Register Name Abbreviation Initial Value* Address* Size Power Down IP Register 2 CPG_PWRDN_IP2 H’0000_0000 H’BB4 Power Down MSTOP Register CPG_PWRDN_MSTOP H’0000_0000 H’BC0 Power Down CLKON Register CPG_PWRDN_CLKON H’0000_0000 H’BC4 Power Down RST Register...
Page 270 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4 Register Descriptions 7.2.4.1 PLLn (SSCG) Standby Control Register (CPG_PLLn_STBY) (n = 1, 4 or 6) This register is used to control the power-saving mode and standby state and enable or disable the SSCG. SSCG_ SSCG_ RESET...
Page 271 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description — Reserved Whenever it is read, 0 is read. The written value will be ignored. SSCG_EN n = 1, 4: SSCG enable or disable setting (see the mode setting table below.* When writing to this bit, set the SSCG_EN_WEN bit to 1 at the same time.
Page 272 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.2 PLLn (SSCG) Output Clock Setting Register 1 (CPG_PLLn_CLK1) (n = 1, 4 or 6) This register is used to specify the frequency division values k, m, and p for SSCG PLLn (n = 1, 4 or 6). —...
Page 273 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description 12 to 1 DIV_NF All 0 Delta-Signa Modulator(DSM) is a bit for configuration.* It can be set within the range of values of 0 to 4095 (decimal) and within the range that satisfies the constraint of Note 1.
Page 274 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.3 PLLn (SSCG) Output Clock Setting Register 2 (CPG_PLLn_CLK2) (n = 1, 4 or 6) This register is used to specify the frequency division value s and SSCG modulation values mfr and mrr for SSCG PLLn (n = 1, 4 or 6).
Page 275 RZ/G3S Group 7. Clock Pulse Generator (CPG) Note 1. The modulation frequency (MF) and modulation ratio (pk-pk) (MR) can be calculated by the following equations. ● Equations MF = PFD input frequency / (Divided ratio × 4) Note: PFD input frequency (fpfd): Input frequency (fstd)/mr ●...
Page 276 RZ/G3S Group 7. Clock Pulse Generator (CPG) Important: For the procedures for setting up the PLL, see Section 7.4.4, Procedures for PLL Setup. Initial Values: The initial values of the registers for PLL1, PLL4 and PLL6 and output clocks are shown below. ●...
Page 277 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.4 PLLn (SSCG) Monitor Register (CPG_PLLn_MON) (n = 1, 2, 3, 4 or 6) This register is used to monitor the state of the SSCG PLLn (n = 1, 2, 3, 4 or 6). —...
Page 278 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.5 PLL1_SEL_SETTING Register (CPG_PLL1_SETTING) This register is used to specify the frequency of PLL1. SEL_PL — — — — — — — — — — — — — — — L1_WE Initial Value R0W1 SEL_PL —...
Page 279 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.6 CPG_OTPPLL0_MON Register (CPG_OTPPLL0_MON) This register indicates the state of the OTP_OTPPLL0[31:0] pins of the CPG. OTP31_ OTP30_ OTP29_ OTP28_ OTP27_ OTP26_ OTP25_ OTP24_ OTP23_ OTP22_ OTP21_ OTP20_ OTP19_ OTP18_ OTP17_ OTP16_ Initial Value —...
Page 280 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.7 CPG_OTPPLL1_MON Register (CPG_OTPPLL1_MON) This register indicates the state of the OTP_OTPPLL1[31:0] pins of the CPG. OTP31_ OTP30_ OTP29_ OTP28_ OTP27_ OTP26_ OTP25_ OTP24_ OTP23_ OTP22_ OTP21_ OTP20_ OTP19_ OTP18_ OTP17_ OTP16_ Initial Value —...
Page 281 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.8 CPG_OTPPLL2_MON Register (CPG_OTPPLL2_MON) This register indicates the state of the OTP_OTPPLL2[31:0] pins of the CPG. OTP31_ OTP30_ OTP29_ OTP28_ OTP27_ OTP26_ OTP25_ OTP24_ OTP23_ OTP22_ OTP21_ OTP20_ OTP19_ OTP18_ OTP17_ OTP16_ Initial Value —...
Page 282 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.9 Division Ratio Setting (PLL1) Register (CPG_PL1_DDIV) This register is used to set the division ratio of the clock for the Cortex-A55. The PLL1 (1,100 MHz) output is used as the source clock. The setting of this register can be dynamically modified while the clock is operating.
Page 283 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.10 Division Ratio Setting (PLL2) Register (CPG_PL2_DDIV) This register is used to set the division ratios of the clocks for the system bus and the IP modules that cannot use SSCG clocks. The PLL2 (up to 1,600 MHz) output is used as the source clock. The setting of this register can be dynamically modified while the clock is operating.
Page 284 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.11 Division Ratio Setting (PLL3) Register (CPG_PL3_DDIV) This register is used to set the division ratios of the clocks for the system bus and the IP modules that can use SSCG clocks. The clock obtained by dividing the output of PLL3 is used as the source clock. The setting of this register can be dynamically modified while the clock is operating.
Page 285 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description 6 to 4 DIVPL3B_SE 000b P2ϕ(DIV_PLL3_100)division ratio setting 000b: 1/1 (100 MHz) 001b: 1/2 (50 MHz) 010b: 1/4 (25 MHz) 011b: 1/8 (12.5 MHz) 100b: 1/32 (3.125 MHz) Others: Setting prohibited —...
Page 286 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.12 Division Ratio Setting (PLL6) Register (CPG_PL6_DDIV) This register is used to set the division ratio of the clock for the Cortex-M33. 1/2 of the PLL6 (500 MHz) output is used as the source clock. The setting of this register can be dynamically modified while the clock is operating.
Page 287 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.13 Division Ratio Setting (SDHI) Register (CPG_SDHI_DDIV) This register is used to set the division ratio of the clock for the SDHI. SEL_SDHIn (n = 0, 1 and 2) output is used as the source clock. The setting of this register can be dynamically modified while the clock is operating.
Page 288 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description DIVSDHI0_S DIV_SDHI0 division ratio setting. 0b: 1/1 (If 800 MHz is selected in the CPG_SDHI_DSEL, setting is prohibited.) 1b: 1/2 R01UH1014EJ0110 Rev.1.10 Page 288 of 3776 Nov 30, 2023...
Page 289 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.14 Division Ratio Setting (OCTA) Register (CPG_OCTA_DDIV) This register is used to set the division ratio of the clock for the OCTA. SEL_OCTA output is used as the source clock. The setting of this register can be dynamically modified while the clock is operating. If 400 MHz is selected in the CPG_OCTA_SSEL, 1/1 setting is prohibited.
Page 290 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.15 Division Ratio Setting (SPI) Register (CPG_SPI_DDIV) This register is used to set the division ratio of the clock for the SPI. SEL_SPI output is used as the source clock. The setting of this register can be dynamically modified while the clock is operating. If 400 MHz is selected in the CPG_SPI_SSEL, 1/1 setting is prohibited.
Page 291 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.16 Source Clock Setting (PLL) Register (CPG_PLL_DSEL) This register is used to switch the clocks for the PLL. SELPL4 — — — — — — — — — — — — — — —...
Page 292 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.17 Source Clock Setting (SDHI) Register (CPG_SDHI_DSEL) This register is used to switch the clocks for the SDHI. The setting of this register can be dynamically modified while the clock is operating. SEL_SD SEL_SD SEL_SD —...
Page 293 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description 1, 0 SEL_SDHI0_ SEL_SDHI0 clock switching 00b: 800 MHz (Be sure to set it to 1/2 in the CPG_SDHI_DDIV) 01b: Setting prohibited 10b: 500 MHz 11b: 266 MHz Note: When 1 is written to the SEL_SDHI2_WEN, SEL_SDHI1_WEN, or SEL_SDHI0_WEN bit placed in the upper 16 bits of this register, the clock switching control begins even if the settings in the lower bits are not changed.
Page 294 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.18 Clock Status Monitor Register (CPG_CLKDIVSTATUS) This register is used to monitor whether clock switching is completed in the dynamically modifiable frequency dividers and selectors. DIV SPI DIVOCT DIVSDH DIVSDH DIVSDH DIVPL6 DIVPL6 —...
Page 295 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description DIVPL3A_ST DIV_PLL3_200 clock switch completion state 0: Switching is completed. 1: Switching is not completed (busy). 7, 6 — Reserved When read, the initial value is read. The written value will be ignored. DIVPL2B_ST DIV_PLL2_100 clock switch completion state 0: Switching is completed.
Page 296 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.19 Clock Status (Selector Setting) Monitor Register (CPG_CLKSELSTATUS) This is a dynamically modifiable selector clock switching completion status monitor register. SELSD SELSD SELSD — — — — — — — — — — —...
Page 297 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description SEL_PLL1 clock switch completion state PL1_STS 0: Switching is completed. 1: Switching is not completed (busy). R01UH1014EJ0110 Rev.1.10 Page 297 of 3776 Nov 30, 2023...
Page 298 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.20 Source Clock Setting Register (CPG_OCTA_SSEL) This is the OCTA source clock switching register. SELOC — — — — — — — — — — — — — — — TA_WE Initial Value R0W1 —...
Page 299 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.21 Source Clock Setting Register (CPG_SPI_SSEL) This is the SPI source clock switching register. SELSPI — — — — — — — — — — — — — — — _WEN Initial Value R0W1 —...
Page 300 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.22 Clock Control Register Cortex-A55 (CPG_CLKON_CA55) This register is used to supply or stop clocks for individual modules. CLK5_O CLK4_O CLK3_O CLK2_O CLK1_O CLK0_O — — — — — — — — — —...
Page 301 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK3_ON The CA55_GICCLK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied. CLK2_ON The CA55_ATCLK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied.
Page 302 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.23 Clock Control Register Cortex-M33 (CPG_CLKON_CM33) This register is used to supply or stop clocks for individual modules. CLK9_O CLK8_O CLK1_O CLK0_O — — — — — — — — — — — —...
Page 303 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.24 Clock Control Register ACPU (CPG_CLKON_SRAM_ACPU) This register is used to supply or stop clocks for individual modules. CLK2_O CLK1_O CLK0_O — — — — — — — — — — — — —...
Page 304 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.25 Clock Control Register MCPU (CPG_CLKON_SRAM_MCPU) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 305 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.26 Clock Control Register GIC600 (CPG_CLKON_GIC600) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 306 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.27 Clock Control Register IA55 (CPG_CLKON_IA55) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 307 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.28 Clock Control Register IM33 (CPG_CLKON_IM33) This register is used to supply or stop clocks for individual modules. CLK9_O CLK8_O CLK1_O CLK0_O — — — — — — — — — — — —...
Page 308 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.29 Clock Control Register MHU (CPG_CLKON_MHU) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 309 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.30 Clock Control Register CST (CPG_CLKON_CST) This register is used to supply or stop clocks for individual modules. CLK13_ CLK12_ CLK11_ CLK10_ CLK9_O CLK8_O CLK7_O CLK6_O CLK5_O CLK4_O CLK3_O CLK2_O CLK1_O CLK0_O — —...
Page 310 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK5_ONWE R0W1 Flag for enabling the writing to the CLK5_ON bit (bit 5) This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. CLK4_ONWE R0W1 Flag for enabling the writing to the CLK4_ON bit (bit 4) This bit is always read as 0.
Page 311 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK5_ON The CST_AHB_CM33_CLK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied. CLK4_ON The CST_APB_CA55_CLK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied.
Page 312 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.31 Clock Control Register SYC (CPG_CLKON_SYC) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 313 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.32 Clock Control Register DMAC_REG (CPG_CLKON_DMAC_REG) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 314 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.33 Clock Control Register GTM (CPG_CLKON_GTM) This register is used to supply or stop clocks for individual modules. CLK7_O CLK6_O CLK5_O CLK4_O CLK3_O CLK2_O CLK1_O CLK0_O — — — — — — — —...
Page 315 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK7_ON The OSTM7_PCLK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied. CLK6_ON The OSTM6_PCLK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied.
Page 316 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.34 Clock Control Register MTU (CPG_CLKON_MTU) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 317 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.35 Clock Control Register POE3 (CPG_CLKON_POE3) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 318 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.36 Clock Control Register GPT (CPG_CLKON_GPT) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 319 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.37 Clock Control Register POEG (CPG_CLKON_POEG) This register is used to supply or stop clocks for individual modules. CLK3_O CLK2_O CLK1_O CLK0_O — — — — — — — — — — — —...
Page 320 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.38 Clock Control Register WDT (CPG_CLKON_WDT) This register is used to supply or stop clocks for individual modules. CLK5_O CLK4_O CLK3_O CLK2_O CLK1_O CLK0_O — — — — — — — — — —...
Page 321 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK4_ON The WDT2_PCLK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied. CLK3_ON The WDT1_CLK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied.
Page 322 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.39 Clock Control Register DDR (CPG_CLKON_DDR) This register is used to supply or stop clocks for individual modules. CLK3_O CLK0_2 CLK1_O CLK0_O — — — — — — — — — — — —...
Page 323 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.40 Clock Control Register SPI (CPG_CLKON_SPI) This register is used to supply or stop clocks for individual modules. CLK3_O CLK2_O CLK1_O CLK0_O — — — — — — — — — — — —...
Page 324 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.41 Clock Control Register SDHI (CPG_CLKON_SDHI) This register is used to supply or stop clocks for individual modules. CLK11_ CLK10_ CLK9_O CLK8_O CLK7_O CLK6_O CLK5_O CLK4_O CLK3_O CLK2_O CLK1_O CLK0_O — — — —...
Page 325 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK3_ONWE R0W1 Flag for enabling the writing to the CLK3_ON bit (bit 3) This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. CLK2_ONWE R0W1 Flag for enabling the writing to the CLK2_ON bit (bit 2) This bit is always read as 0.
Page 326 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK0_ON The SDHI0_IMCLK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied. R01UH1014EJ0110 Rev.1.10 Page 326 of 3776 Nov 30, 2023...
Page 327 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.42 Clock Control Register SSI (CPG_CLKON_SSI) This register is used to supply or stop clocks for individual modules. CLK7_O CLK6_O CLK5_O CLK4_O CLK3_O CLK2_O CLK1_O CLK0_O — — — — — — — —...
Page 328 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK7_ON The SSI3_PCLK_SFR clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied. CLK6_ON The SSI3_PCLK2 clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied.
Page 329 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.43 Clock Control Register SRC (CPG_CLKON_SRC) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 330 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.44 Clock Control Register USB (CPG_CLKON_USB) This register is used to supply or stop clocks for individual modules. CLK3_O CLK2_O CLK1_O CLK0_O — — — — — — — — — — — —...
Page 331 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.45 Clock Control Register ETH (CPG_CLKON_ETH) This register is used to supply or stop clocks for individual modules. CLK9_O CLK8_O CLK1_O CLK0_O — — — — — — — — — — — —...
Page 332 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.46 Clock Control Register I2C (CPG_CLKON_I2C) This register is used to supply or stop clocks for individual modules. CLK3_O CLK2_O CLK1_O CLK0_O — — — — — — — — — — — —...
Page 333 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.47 Clock Control Register SCIF (CPG_CLKON_SCIF) This register is used to supply or stop clocks for individual modules. CLK5_O CLK4_O CLK3_O CLK2_O CLK1_O CLK0_O — — — — — — — — — —...
Page 334 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK3_ON The SCIF3_CLK_PCK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied. CLK2_ON The SCIF2_CLK_PCK clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied.
Page 335 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.48 Clock Control Register SCI (CPG_CLKON_SCI) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 336 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.49 Clock Control Register IRDA (CPG_CLKON_IRDA) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 337 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.50 Clock Control Register RSPI (CPG_CLKON_RSPI) This register is used to supply or stop clocks for individual modules. CLK4_O CLK3_O CLK2_O CLK1_O CLK0_O — — — — — — — — — — —...
Page 338 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK0_ON The RSPI0_CLKB clock is supplied or stopped. 0: Clock is stopped. 1: Clock is supplied. R01UH1014EJ0110 Rev.1.10 Page 338 of 3776 Nov 30, 2023...
Page 339 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.51 Clock Control Register CANFD (CPG_CLKON_CANFD) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 340 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.52 Clock Control Register GPIO (CPG_CLKON_GPIO) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 341 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.53 Clock Control Register ADC (CPG_CLKON_ADC) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 342 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.54 Clock Control Register TSU (CPG_CLKON_TSU) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 343 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.55 Clock Control Register AXI_ACPU_BUS (CPG_CLKON_AXI_ACPU_BUS) This register is used to supply or stop clocks for individual modules. The clocks listed in this register are not listed in the separate clock list. CLK6_O CLK5_O CLK4_O CLK3_O...
Page 344 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK5_ON 0: Clock is stopped. 1: Clock is supplied. CLK4_ON 0: Clock is stopped. 1: Clock is supplied. CLK3_ON 0: Clock is stopped. 1: Clock is supplied. CLK2_ON 0: Clock is stopped.
Page 345 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.56 Clock Control Register AXI_MCPU_BUS (CPG_CLKON_AXI_MCPU_BUS) This register is used to supply or stop clocks for individual modules. The clocks listed in this register are not listed in the separate clock list. CLK15_ CLK14_ CLK12_ CLK11_...
Page 346 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK6_ONWE R0W1 Flag for enabling the writing to the CLK6_ON bit (bit 6) This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. CLK5_ONWE R0W1 Flag for enabling the writing to the CLK5_ON bit (bit 5) This bit is always read as 0.
Page 347 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK4_ON 0: Clock is stopped. 1: Clock is supplied. CLK3_ON 0: Clock is stopped. 1: Clock is supplied. CLK2_ON 0: Clock is stopped. 1: Clock is supplied. CLK1_ON 0: Clock is stopped.
Page 348 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.57 Clock Control Register AXI_COM_BUS (CPG_CLKON_AXI_COM_BUS) This register is used to supply or stop clocks for individual modules. The clocks listed in this register are not listed in the separate clock list. CLK9_O CLK8_O CLK1_O CLK0_O...
Page 349 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.58 Clock Control Register PERI_COM (CPG_CLKON_PERI_COM) This register is used to supply or stop clocks for individual modules. The clocks listed in this register are not listed in the separate clock list. CLK9_O CLK8_O CLK1_O CLK0_O...
Page 350 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.59 Clock Control Register REG1_BUS (CPG_CLKON_REG1_BUS) This register is used to supply or stop clocks for individual modules. The clocks listed in this register are not listed in the separate clock list. CLK1_O CLK0_O —...
Page 351 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.60 Clock Control Register REG0_BUS (CPG_CLKON_REG0_BUS) This register is used to supply or stop clocks for individual modules. The clocks listed in this register are not listed in the separate clock list. CLK3_O CLK2_O CLK1_O CLK0_O...
Page 352 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.61 Clock Control Register PERI_CPU (CPG_CLKON_PERI_CPU) This register is used to supply or stop clocks for individual modules. The clocks listed in this register are not listed in the separate clock list. CLK7_O CLK6_O CLK5_O CLK4_O...
Page 353 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description 15 to 8 — All 0 Reserved Whenever it is read, 0 is read. The written value will be ignored. CLK7_ON 0: Clock is stopped. 1: Clock is supplied. CLK6_ON 0: Clock is stopped.
Page 354 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.62 Clock Control Register PERI_DDR (CPG_CLKON_PERI_DDR) This register is used to supply or stop clocks for individual modules. The clocks listed in this register are not listed in the separate clock list. CLK0_O —...
Page 355 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.63 Clock Control Register AXI_TZCDDR (CPG_CLKON_AXI_TZCDDR) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 356 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.64 Clock Control Register OCTA (CPG_CLKON_OCTA) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 357 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.65 Clock Control Register OTFDE_DDR (CPG_CLKON_OTFDE_DDR) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 358 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.66 Clock Control Register OTFDE_SPI (CPG_CLKON_OTFDE_SPI) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 359 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.67 Clock Control Register PDM (CPG_CLKON_PDM) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 360 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.68 Clock Control Register PCI (CPG_CLKON_PCI) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 361 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.69 Clock Control Register SPDIF (CPG_CLKON_SPDIF) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 362 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.70 Clock Control Register I3C (CPG_CLKON_I3C) This register is used to supply or stop clocks for individual modules. CLK1_O CLK0_O — — — — — — — — — — — — — —...
Page 363 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.71 Clock Control Register VBAT (CPG_CLKON_VBAT) This register is used to supply or stop clocks for individual modules. CLK0_O — — — — — — — — — — — — — — —...
Page 364 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.72 Clock Monitor Register Cortex-A55 (CPG_CLKMON_CA55) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 365 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.73 Clock Monitor Register Cortex-M33 (CPG_CLKMON_CM33) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 366 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.74 Clock Monitor Register SRAM_ACPU (CPG_CLKMON_SRAM_ACPU) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 367 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.75 Clock Monitor Register SRAM_MCPU (CPG_CLKMON_SRAM_MCPU) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 368 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.76 Clock Monitor Register GIC600 (CPG_CLKMON_GIC600) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 369 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.77 Clock Monitor Register IA55 (CPG_CLKMON_IA55) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 370 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.78 Clock Monitor Register IM33 (CPG_CLKMON_IM33) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 371 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.79 Clock Monitor Register MHU (CPG_CLKMON_MHU) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 372 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.80 Clock Monitor Register CST (CPG_CLKMON_CST) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 373 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK2_MON The state of the CST_APB_SB_CLK clock is monitored. 0: Clock is not supplied. 1: Clock is supplied. CLK1_MON The state of the CST_TS_CLK clock is monitored. 0: Clock is not supplied. 1: Clock is supplied.
Page 374 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.81 Clock Monitor Register SYC (CPG_CLKMON_SYC) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 375 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.82 Clock Monitor Register DMAC_REG (CPG_CLKMON_DMAC_REG) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 376 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.83 Clock Monitor Register GTM (CPG_CLKMON_GTM) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 377 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.84 Clock Monitor Register MTU (CPG_CLKMON_MTU) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 378 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.85 Clock Monitor Register POE3 (CPG_CLKMON_POE3) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 379 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.86 Clock Monitor Register GPT (CPG_CLKMON_GPT) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 380 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.87 Clock Monitor Register POEG (CPG_CLKMON_POEG) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 381 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.88 Clock Monitor Register WDT (CPG_CLKMON_WDT) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 382 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.89 Clock Monitor Register DDR (CPG_CLKMON_DDR) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 383 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.90 Clock Monitor Register SPI (CPG_CLKMON_SPI) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 384 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.91 Clock Monitor Register SDHI (CPG_CLKMON_SDHI) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 385 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK0_MON The state of the SDHI0_IMCLK clock is monitored. 0: Clock is not supplied. 1: Clock is supplied. R01UH1014EJ0110 Rev.1.10 Page 385 of 3776 Nov 30, 2023...
Page 386 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.92 Clock Monitor Register SSI (CPG_CLKMON_SSI) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 387 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.93 Clock Monitor Register SRC (CPG_CLKMON_SRC) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 388 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.94 Clock Monitor Register USB (CPG_CLKMON_USB) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 389 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.95 Clock Monitor Register ETH (CPG_CLKMON_ETH) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 390 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.96 Clock Monitor Register I2C (CPG_CLKMON_I2C) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 391 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.97 Clock Monitor Register SCIF (CPG_CLKMON_SCIF) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 392 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.98 Clock Monitor Register SCI (CPG_CLKMON_SCI) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 393 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.99 Clock Monitor Register IRDA (CPG_CLKMON_IRDA) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 394 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.100 Clock Monitor Register RSPI (CPG_CLKMON_RSPI) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 395 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.101 Clock Monitor Register CANFD (CPG_CLKMON_CANFD) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 396 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.102 Clock Monitor Register GPIO (CPG_CLKMON_GPIO) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 397 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.103 Clock Monitor Register ADC (CPG_CLKMON_ADC) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 398 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.104 Clock Monitor Register TSU (CPG_CLKMON_TSU) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 399 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.105 Clock Monitor Register AXI_ACPU_BUS (CPG_CLKMON_AXI_ACPU_BUS) This register is used to monitor the state of the clocks supplied to individual modules. The clocks listed in this register are not listed in the separate clock list. —...
Page 400 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.106 Clock Monitor Register AXI_MCPU_BUS (CPG_CLKMON_AXI_MCPU_BUS) This register is used to monitor the state of the clocks supplied to individual modules. The clocks listed in this register are not listed in the separate clock list. —...
Page 401 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description CLK0_MON 0: Clock is not supplied. 1: Clock is supplied. R01UH1014EJ0110 Rev.1.10 Page 401 of 3776 Nov 30, 2023...
Page 402 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.107 Clock Monitor Register AXI_COM_BUS (CPG_CLKMON_AXI_COM_BUS) This register is used to monitor the state of the clocks supplied to individual modules. The clocks listed in this register are not listed in the separate clock list. —...
Page 403 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.108 Clock Monitor Register PERI_COM (CPG_CLKMON_PERI_COM) This register is used to monitor the state of the clocks supplied to individual modules. The clocks listed in this register are not listed in the separate clock list. —...
Page 404 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.109 Clock Monitor Register REG1_BUS (CPG_CLKMON_REG1_BUS) This register is used to monitor the state of the clocks supplied to individual modules. The clocks listed in this register are not listed in the separate clock list. —...
Page 405 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.110 Clock Monitor Register REG0_BUS (CPG_CLKMON_REG0_BUS) This register is used to monitor the state of the clocks supplied to individual modules. The clocks listed in this register are not listed in the separate clock list. —...
Page 406 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.111 Clock Monitor Register PERI_CPU (CPG_CLMKON_PERI_CPU) This register is used to monitor the state of the clocks supplied to individual modules. The clocks listed in this register are not listed in the separate clock list. —...
Page 407 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.112 Clock Monitor Register PERI_DDR (CPG_CLKMON_PERI_DDR) This register is used to monitor the state of the clocks supplied to individual modules. The clocks listed in this register are not listed in the separate clock list. —...
Page 408 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.113 Clock Monitor Register AXI_TZCDDR (CPG_CLKMON_AXI_TZCDDR) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 409 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.114 Clock Monitor Register OCTA (CPG_CLKMON_OCTA) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 410 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.115 Clock Monitor Register OTFDE_DDR (CPG_CLKMON_OTFDE_DDR) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 411 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.116 Clock Monitor Register OTFDE_SPI (CPG_CLKMON_OTFDE_SPI) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 412 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.117 Clock Monitor Register PDM (CPG_CLKMON_PDM) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 413 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.118 Clock Monitor Register PCI (CPG_CLKMON_PCI) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 414 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.119 Clock Monitor Register SPDIF (CPG_CLKMON_SPDIF) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 415 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.120 Clock Monitor Register I3C (CPG_CLKMON_I3C) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 416 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.121 Clock Monitor Register VBAT (CPG_CLKMON_VBAT) This register is used to monitor the state of the clocks supplied to individual modules. — — — — — — — — — — — — —...
Page 417 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.122 Reset Control Register Cortex-A55 (CPG_RST_CA55) This register is used to control the reset signals for individual modules. UNIT12 UNIT11 UNIT10 UNIT9_ UNIT8_ UNIT7_ UNIT6_ UNIT5_ UNIT4_ UNIT2_ UNIT0_ — — — _RSTW _RSTW _RSTW RSTWE...
Page 418 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description UNIT4_RST R0W1 Flag for enabling the writing to the UNIT4_RSTB bit (bit 4) This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. —...
Page 419 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description UNIT2_RSTB 1b The CA55_RST3_0 reset terminal is controlled. 0: Reset signal is applied (reset state). 1: Reset signal is stopped (released from the reset state). — Reserved When read, the initial value is read. When writing, be sure to write the initial value. Operation is not guaranteed if a value other than the initial value is written.
Page 420 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.123 Reset Control Register Cortex-M33 (CPG_RST_CM33) This register is used to control the reset signals for individual modules. UNIT10 UNIT9_ UNIT8_ UNIT2_ UNIT1_ UNIT0_ — — — — — _RSTW RSTWE RSTWE — —...
Page 421 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description UNIT8_RSTB 0b The CM33_FPU_NPORESET reset terminal is controlled. 0: Reset signal is applied (reset state). 1: Reset signal is stopped (released from the reset state). 7 to 3 —...
Page 422 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.124 Reset Control Register SRAM_ACPU (CPG_RST_SRAM_ACPU) This register is used to control the reset signals for individual modules. UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — — — — —...
Page 423 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.125 Reset Control Register SRAM_MCPU (CPG_RST_SRAM_MCPU) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 424 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.126 Reset Control Register GIC600 (CPG_RST_GIC600) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 425 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.127 Reset Control Register IA55 (CPG_RST_IA55) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 426 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.128 Reset Control Register IM33 (CPG_RST_IM33) This register is used to control the reset signals for individual modules. UNIT8_ UNIT0_ — — — — — — — RSTWE — — — — — —...
Page 427 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.129 Reset Control Register MHU (CPG_RST_MHU) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 428 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.130 Reset Control Register DMAC (CPG_RST_DMAC) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 429 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.131 Reset Control Register SYC (CPG_RST_SYC) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 430 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.132 Reset Control Register GTM (CPG_RST_GTM) This register is used to control the reset signals for individual modules. UNIT7_ UNIT6_ UNIT5_ UNIT4_ UNIT3_ UNIT2_ UNIT1_ UNIT0_ — — — — — — — —...
Page 431 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description UNIT7_RSTB 0b The OSTM7_PRESETZ reset terminal is controlled. 0: Reset signal is applied (reset state). 1: Reset signal is stopped (released from the reset state). UNIT6_RSTB 0b The OSTM6_PRESETZ reset terminal is controlled. 0: Reset signal is applied (reset state).
Page 432 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.133 Reset Control Register MTU (CPG_RST_MTU) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 433 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.134 Reset Control Register POE3 (CPG_RST_POE3) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 434 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.135 Reset Control Register GPT (CPG_RST_GPT) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 435 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.136 Reset Control Register POEG (CPG_RST_POEG) This register is used to control the reset signals for individual modules. UNIT3_ UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — — — —...
Page 436 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.137 Reset Control Register WDT (CPG_RST_WDT) This register is used to control the reset signals for individual modules. UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — — — — —...
Page 437 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.138 Reset Control Register DDR (CPG_RST_DDR) This register is used to control the reset signals for individual modules. UNIT8_ UNIT7_ UNIT6_ UNIT3_ UNIT2_ UNIT1_ UNIT0_ — — — — — — — RSTWE RSTWE RSTWE —...
Page 438 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description UNIT8_RSTB 0b The DDR_PWROKIN reset terminal is controlled. 0: Reset signal is applied (reset state). 1: Reset signal is stopped (released from the reset state). UNIT7_RSTB 0b The DDR_RESET reset terminal is controlled. 0: Reset signal is applied (reset state).
Page 439 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.139 Reset Control Register SPI (CPG_RST_SPI) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 440 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.140 Reset Control Register SDHI (CPG_RST_SDHI) This register is used to control the reset signals for individual modules. UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — — — — —...
Page 441 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.141 Reset Control Register SSIF (CPG_RST_SSIF) This register is used to control the reset signals for individual modules. UNIT3_ UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — — — —...
Page 442 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.142 Reset Control Register SRC (CPG_RST_SRC) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 443 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.143 Reset Control Register USB (CPG_RST_USB) This register is used to control the reset signals for individual modules. UNIT3_ UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — — — —...
Page 444 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.144 Reset Control Register ETH (CPG_RST_ETH) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 445 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.145 Reset Control Register I2C (CPG_RST_I2C) This register is used to control the reset signals for individual modules. UNIT3_ UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — — — —...
Page 446 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.146 Reset Control Register SCIF (CPG_RST_SCIF) This register is used to control the reset signals for individual modules. UNIT5_ UNIT4_ UNIT3_ UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — —...
Page 447 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description UNIT3_RSTB 0b The SCIF3_RST_SYSTEM_N reset terminal is controlled. 0: Reset signal is applied (reset state). 1: Reset signal is stopped (released from the reset state). UNIT2_RSTB 0b The SCIF2_RST_SYSTEM_N reset terminal is controlled. 0: Reset signal is applied (reset state).
Page 448 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.147 Reset Control Register SCI (CPG_RST_SCI) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 449 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.148 Reset Control Register IRDA (CPG_RST_IRDA) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 450 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.149 Reset Control Register RSPI (CPG_RST_RSPI) This register is used to control the reset signals for individual modules. UNIT4_ UNIT3_ UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — — —...
Page 451 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description UNIT0_RSTB 0b The RSPI0_RST reset terminal is controlled. 0: Reset signal is applied (reset state). 1: Reset signal is stopped (released from the reset state). R01UH1014EJ0110 Rev.1.10 Page 451 of 3776 Nov 30, 2023...
Page 452 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.150 Reset Control Register CANFD (CPG_RST_CANFD) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 453 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.151 Reset Control Register GPIO (CPG_RST_GPIO) This register is used to control the reset signals for individual modules. UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — — — — —...
Page 454 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.152 Reset Control Register ADC (CPG_RST_ADC) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 455 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.153 Reset Control Register TSU (CPG_RST_TSU) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 456 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.154 Reset Control Register AXI_ACPU_BUS (CPG_RST_AXI_ACPU_BUS) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 457 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.155 Reset Control Register AXI_MCPU_BUS (CPG_RST_AXI_MCPU_BUS) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 458 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.156 Reset Control Register AXI_COM_BUS (CPG_RST_AXI_COM_BUS) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 459 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.157 Reset Control Register PERI_COM (CPG_RST_PERI_COM) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 460 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.158 Reset Control Register REG1_BUS (CPG_RST_REG1_BUS) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 461 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.159 Reset Control Register REG0_BUS (CPG_RST_REG0_BUS) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 462 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.160 Reset Control Register PERI_CPU (CPG_RST_PERI_CPU) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 463 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.161 Reset Control Register PERI_DDR (CPG_RST_PERI_DDR) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 464 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.162 Reset Control Register AXI_TZCDDR (CPG_RST_AXI_TZCDDR) This register is used to control the reset signals for individual modules. UNIT3_ UNIT2_ UNIT1_ UNIT0_ — — — — — — — — — — — —...
Page 465 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description UNIT0_RSTB 1b The BUS_TZCDDR_PRESETN reset terminal is controlled. 0: Reset signal is applied (reset state). 1: Reset signal is stopped (released from the reset state). R01UH1014EJ0110 Rev.1.10 Page 465 of 3776 Nov 30, 2023...
Page 466 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.163 Reset Control Register OCTA (CPG_RST_OCTA) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 467 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.164 Reset Control Register OTFDE_DDR (CPG_RST_OTFDE_DDR) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 468 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.165 Reset Control Register OTFDE_SPI (CPG_RST_OTFDE_SPI) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 469 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.166 Reset Control Register PDM (CPG_RST_PDM) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 470 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.167 Reset Control Register PCI (CPG_RST_PCI) This register is used to control the reset signals for individual modules. UNIT6_ UNIT5_ UNIT4_ UNIT3_ UNIT2_ UNIT1_ UNIT0_ — — — — — — — — —...
Page 471 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description UNIT5_RSTB 0b The PCI_RST_CFG_B reset terminal is controlled. 0: Reset signal is applied (reset state). 1: Reset signal is stopped (released from the reset state). UNIT4_RSTB 0b The PCI_RST_RSM_B reset terminal is controlled. 0: Reset signal is applied (reset state).
Page 472 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.168 Reset Control Register SPDIF (CPG_RST_SPDIF) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 473 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.169 Reset Control Register I3C (CPG_RST_I3C) This register is used to control the reset signals for individual modules. UNIT1_ UNIT0_ — — — — — — — — — — — — — —...
Page 474 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.170 Reset Control Register VBAT (CPG_RST_VBAT) This register is used to control the reset signals for individual modules. UNIT0_ — — — — — — — — — — — — — — —...
Page 475 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.171 Reset Monitor Register Cortex-CA55 (CPG_RSTMON_CA55) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 476 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description — Reserved When read, the initial value is read. When writing, be sure to write the initial value. Operation is not guaranteed if a value other than the initial value is written. RST0_MON The state of the CA55_RST1_0 reset signal is monitored.
Page 477 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.172 Reset Monitor Register Cortex-M33 (CPG_RSTMON_CM33) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 478 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.173 Reset Monitor Register SRAM_ACPU (CPG_RSTMON_SRAM_ACPU) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 479 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.174 Reset Monitor Register SRAM_MCPU (CPG_RSTMON_SRAM_MCPU) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 480 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.175 Reset Monitor Register GIC600 (CPG_RSTMON_GIC600) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 481 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.176 Reset Monitor Register IA55 (CPG_RSTMON_IA55) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 482 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.177 Reset Monitor Register IM33 (CPG_RSTMON_IM33) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 483 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.178 Reset Monitor Register MHU (CPG_RSTMON_MHU) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 484 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.179 Reset Monitor Register DMAC (CPG_RSTMON_DMAC) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 485 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.180 Reset Monitor Register SYC (CPG_RSTMON_SYC) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 486 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.181 Reset Monitor Register GTM (CPG_RSTMON_GTM) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 487 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.182 Reset Monitor Register MTU (CPG_RSTMON_MTU) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 488 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.183 Reset Monitor Register POE3 (CPG_RSTMON_POE3) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 489 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.184 Reset Monitor Register GPT (CPG_RSTMON_GPT) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 490 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.185 Reset Monitor Register POEG (CPG_RSTMON_POEG) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 491 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.186 Reset Monitor Register WDT (CPG_RSTMON_WDT) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 492 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.187 Reset Monitor Register DDR (CPG_RSTMON_DDR) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 493 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.188 Reset Monitor Register SPI (CPG_RSTMON_SPI) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 494 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.189 Reset Monitor Register SDHI (CPG_RSTMON_SDHI) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 495 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.190 Reset Monitor Register SSIF (CPG_RSTMON_SSIF) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 496 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.191 Reset Monitor Register SRC (CPG_RSTMON_SRC) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 497 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.192 Reset Monitor Register USB (CPG_RSTMON_USB) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 498 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.193 Reset Monitor Register ETH (CPG_RSTMON_ETH) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 499 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.194 Reset Monitor Register I2C (CPG_RSTMON_I2C) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 500 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.195 Reset Monitor Register SCIF (CPG_RSTMON_SCIF) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 501 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.196 Reset Monitor Register SCI (CPG_RSTMON_SCI) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 502 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.197 Reset Monitor Register IRDA (CPG_RSTMON_IRDA) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 503 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.198 Reset Monitor Register RSPI (CPG_RSTMON_RSPI) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 504 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.199 Reset Monitor Register CANFD (CPG_RSTMON_CANFD) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 505 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.200 Reset Monitor Register GPIO (CPG_RSTMON_GPIO) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 506 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.201 Reset Monitor Register ADC (CPG_RSTMON_ADC) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 507 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.202 Reset Monitor Register TSU (CPG_RSTMON_TSU) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 508 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.203 Reset Monitor Register AXI_ACPU_BUS (CPG_RSTMON_AXI_ACPU_BUS) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 509 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.204 Reset Monitor Register AXI_MCPU_BUS (CPG_RSTMON_AXI_MCPU_BUS) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 510 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.205 Reset Monitor Register AXI_COM_BUS (CPG_RSTMON_AXI_COM_BUS) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 511 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.206 Reset Monitor Register PERI_COM (CPG_RSTMON_PERI_COM) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 512 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.207 Reset Monitor Register REG1_BUS (CPG_RSTMON_REG1_BUS) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 513 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.208 Reset Monitor Register REG0_BUS (CPG_RSTMON_REG0_BUS) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 514 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.209 Reset Monitor Register PERI_CPU (CPG_RSTMON_PERI_CPU) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 515 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.210 eset Monitor Register PERI_DDR (CPG_RSTMON_PERI_DDR) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 516 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.211 Reset Monitor Register AXI_TZCDDR (CPG_RSTMON_AXI_TZCDDR) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 517 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.212 Reset Monitor Register OCTA (CPG_RSTMON_OCTA) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 518 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.213 Reset Monitor Register OTFDE_DDR (CPG_RSTMON_OTFDE_DDR) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 519 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.214 Reset Monitor Register OTFDE_SPI (CPG_RSTMON_OTFDE_SPI) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 520 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.215 Reset Monitor Register PDM (CPG_RSTMON_PDM) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 521 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.216 Reset Monitor Register PCI (CPG_RSTMON_PCI) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 522 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.217 Reset Monitor Register SPDIF (CPG_RSTMON_SPDIF) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 523 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.218 Reset Monitor Register I3C (CPG_RSTMON_I3C) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 524 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.219 Reset Monitor Register VBAT (CPG_RSTMON_VBAT) This register is used to monitor the reset signals of individual modules. — — — — — — — — — — — — — — — —...
Page 525 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.220 WDT Overflow System Reset Register (CPG_WDTOVF_RST) After the release from a system reset applied by the WDT reset circuit in response to a reset request such as a WDT overflow, this register can be used to identify the WDT channel that generated the reset request. If a system reset is not applied according to the WDTRSTSEL register setting, the WDT is not reset and the source of the reset request can be identified by checking the interrupt from the WDT and the status register.
Page 526 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description WDTOVF0 The system reset generated WDT channel 0 for Cortex-A55 Core 0 is indicated. 0: System reset has not been generated by WDT channel 0 for Cortex-A55 Core 0. 1: System reset has been generated by WDT channel 0 for Cortex-A55 Core 0.
Page 527 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.221 WDT Reset Selector Register (CPG_WDTRST_SEL) This register is used to mask reset requests from the WDT. WDTRS WDTRS WDTRS WDTRS WDTRS WDTRS WDTRS WDTRS WDTRS — — — — — TSEL10 TSEL9_ TSEL8_ —...
Page 528 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description WDTRSTSEL R0W1 Flag for enabling the writing to the WDTRSTSEL1 bit (bit 1) 1_WEN This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. WDTRSTSEL R0W1 Flag for enabling the writing to the WDTRSTSEL0 bit (bit 0) 0_WEN...
Page 529 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.222 Cortex-A55 Cluster Power Status Monitor Register (CPG_CLUSTER_PCHMON) A handshake through the P-Channel is necessary before a warm reset in the Cortex-A55. This register is monitored by the CPU for software control of the handshake. —...
Page 530 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.223 Cortex-A55 Cluster Power Status Control Register (CPG_CLUSTER_PCHCTL) A handshake through the P-Channel is necessary before a warm reset in the Cortex-A55. This register is used for software control of the handshake. — —...
Page 531 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.224 Cortex-A55 Core 0 Power Status Monitor Register (CPG_CORE0_PCHMON) A handshake through the P-Channel is necessary before a warm reset in the Cortex-A55. This register is monitored by the CPU for software control of the handshake. —...
Page 532 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.225 Cortex-A55 Core 0 Power Status Control Register (CPG_CORE0_PCHCTL) A handshake through the P-Channel is necessary before a warm reset in the Cortex-A55. This register is used for software control of the handshake. —...
Page 533 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.226 MSTOP Register ACPU (CPG_BUS_ACPU_MSTOP) This register indicates the stop state of individual modules. MSTOP — — — — — — — — — — — — — — — 0_ON_ Initial Value R0W1 MSTOP —...
Page 534 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.227 MSTOP Register MCPU1 (CPG_BUS_MCPU1_MSTOP) This register indicates the stop state of individual modules. MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP 15_ON_ 14_ON_ 13_ON_ 12_ON_ 11_ON_ 10_ON_...
Page 535 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP6_ON R0W1 Flag for enabling the writing to the MSTOP6_ON bit (bit 6) _WEN This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. MSTOP5_ON R0W1 Flag for enabling the writing to the MSTOP5_ON bit (bit 5) _WEN...
Page 536 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP7_ON 0b The state of BUS_MCPU_MSTOP5_MHPOEGC operation is indicated. 0: Normal operation 1: Module stop state (MSTP) MSTOP6_ON 0b The state of BUS_MCPU_MSTOP4_MHPOEGB operation is indicated. 0: Normal operation 1: Module stop state (MSTP) MSTOP5_ON 0b The state of BUS_MCPU_MSTOP3_MHPOEGA operation is indicated.
Page 537 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.228 MSTOP Register MCPU2 (CPG_BUS_MCPU2_MSTOP) This register indicates the stop state of individual modules. MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP 15_ON_ 14_ON_ 13_ON_ 12_ON_ 11_ON_ 10_ON_...
Page 538 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP6_ON R0W1 Flag for enabling the writing to the MSTOP6_ON bit (bit 6) _WEN This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. MSTOP5_ON R0W1 Flag for enabling the writing to the MSTOP5_ON bit (bit 5) _WEN...
Page 539 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP7_ON 0b The state of BUS_MCPU_MSTOP21_MHSCI_0 operation is indicated. 0: Normal operation 1: Module stop state (MSTP) MSTOP6_ON 0b The state of BUS_MCPU_MSTOP20_MHIRDA operation is indicated. 0: Normal operation 1: Module stop state (MSTP) MSTOP5_ON 0b The state of BUS_MCPU_MSTOP19_MHSCIF_4 operation is indicated.
Page 540 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.229 MSTOP Register PERI_COM (CPG_BUS_PERI_COM_MSTOP) This register indicates the stop state of individual modules. MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP — — — — 11_ON_ 10_ON_ 9_ON_ 8_ON_ 7_ON_ 6_ON_...
Page 541 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP3_ON R0W1 Flag for enabling the writing to the MSTOP3_ON bit (bit 3) _WEN This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. MSTOP2_ON R0W1 Flag for enabling the writing to the MSTOP2_ON bit (bit 2) _WEN...
Page 542 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP0_ON 0b The state of BUS_PERI_COM_MSTOP0_MXSDHI_0 operation is indicated. 0: Normal operation 1: Module stop state (MSTP) R01UH1014EJ0110 Rev.1.10 Page 542 of 3776 Nov 30, 2023...
Page 543 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.230 MSTOP Register PERI_CPU (CPG_BUS_PERI_CPU_MSTOP) This register indicates the stop state of individual modules. MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP 15_ON_ 14_ON_ 13_ON_ 12_ON_ 11_ON_ 10_ON_ 9_ON_...
Page 544 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP6_ON R0W1 Flag for enabling the writing to the MSTOP6_ON bit (bit 6) _WEN This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. —...
Page 545 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP7_ON 0b The state of BUS_PERI_CPU_MSTOP7_MPTZC_0 operation is indicated. 0: Normal operation 1: Module stop state (MSTP) MSTOP6_ON 0b The state of BUS_PERI_CPU_MSTOP6_MHGPIO operation is indicated. 0: Normal operation 1: Module stop state (MSTP) —...
Page 546 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.231 MSTOP Register PERI_DDR (CPG_BUS_PERI_DDR_MSTOP) This register indicates the stop state of individual modules. MSTOP MSTOP — — — — — — — — — — — — — — 1_ON_ 0_ON_ Initial Value R0W1 R0W1 MSTOP...
Page 547 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.232 MSTOP Register REG0 (CPG_BUS_REG0_MSTOP) This register indicates the stop state of individual modules. MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP — — — — 11_ON_ 10_ON_ 9_ON_ 8_ON_ 7_ON_ 6_ON_ 5_ON_...
Page 548 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description — Reserved When read, the initial value is read. When writing, be sure to write the initial value. Operation is not guaranteed if a value other than the initial value is written. MSTOP2_ON R0W1 Flag for enabling the writing to the MSTOP2_ON bit (bit 2) _WEN...
Page 549 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP0_ON 0b The state of BUS_REG0_MSTOP_MPWDT_0 operation is indicated. 0: Normal operation 1: Module stop state (MSTP) R01UH1014EJ0110 Rev.1.10 Page 549 of 3776 Nov 30, 2023...
Page 550 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.233 MSTOP Register REG1 (CPG_BUS_REG1_MSTOP) This register indicates the stop state of individual modules. MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP — — — — — — — — — 6_ON_ 5_ON_ — 3_ON_ 2_ON_ 1_ON_ 0_ON_...
Page 551 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description — Reserved When read, the initial value is read. When writing, be sure to write the initial value. Operation is not guaranteed if a value other than the initial value is written. MSTOP6_ON 0b The state of BUS_REG1_MSTOP_MPRSIPG_OTP operation is indicated.
Page 552 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.234 MSTOP Register TZCDDR (CPG_BUS_TZCDDR_MSTOP) This register indicates the stop state of individual modules. MSTOP MSTOP MSTOP — — — — — — — — — — — — — 2_ON_ 1_ON_ 0_ON_ Initial Value R0W1 R0W1...
Page 553 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.235 MSTOP Register MHU (CPG_MHU_MSTOP) This register indicates the stop state of individual modules. MSTOP — — — — — — — — — — — — — — — 0_ON_ Initial Value R0W1 MHU_M —...
Page 554 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.236 MSTOP Register MCPU3 (CPG_BUS_MCPU3_MSTOP) This register indicates the stop state of individual modules. MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP — — — — — 10_ON_ 9_ON_ 8_ON_ 7_ON_ 6_ON_ 5_ON_...
Page 555 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP2_ON R0W1 Flag for enabling the writing to the MSTOP2_ON bit (bit 2) _WEN This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. MSTOP1_ON R0W1 Flag for enabling the writing to the MSTOP1_ON bit (bit 1) _WEN...
Page 556 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.237 MSTOP Register BUS_PERI_CPU2 (CPG_BUS_PERI_CPU2_MSTOP) This register indicates the stop state of individual modules. MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP MSTOP — — — — — — 9_ON_ 8_ON_ 7_ON_ 6_ON_ 5_ON_ 4_ON_...
Page 557 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description MSTOP1_ON R0W1 Flag for enabling the writing to the MSTOP1_ON bit (bit 1) _WEN This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. MSTOP0_ON R0W1 Flag for enabling the writing to the MSTOP0_ON bit (bit 0) _WEN...
Page 558 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.238 Power Down IP Register 1 (CPG_PWRDN_IP1) This register indicates the stop state of individual modules. PWRDN PWRDN PWRDN PWRDN PWRDN PWRDN PWRDN PWRDN PWRDN PWRDN PWRDN PWRDN PWRDN PWRDN PWRDN 15_ON_ 14_ON_ 13_ON_ 12_ON_ 11_ON_...
Page 559 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description PWRDN6_O R0W1 Flag for enabling the writing to the PWRDN6_ON bit (bit 6) N_WEN This bit is always read as 0. 0: Writing is disabled. 1: Writing is enabled. PWRDN5_O R0W1 Flag for enabling the writing to the PWRDN5_ON bit (bit 5) N_WEN...
Page 560 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description — Reserved Whenever it is read, 0 is read. The written value will be ignored. PWRDN6_O Controls power down for WDT(Ch2) in Power Down mode. 0: Not subject to power down 1: Subject to power down PWRDN5_O Controls power down for WDT(Ch0) in Power Down mode.
Page 561 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.239 Power Down IP Register 2 (CPG_PWRDN_IP2) This register indicates the stop state of individual modules. PWRDN PWRDN PWRDN PWRDN PWRDN — — — — — — — — — — — 4_ON_ 3_ON_ 2_ON_ 1_ON_...
Page 562 RZ/G3S Group 7. Clock Pulse Generator (CPG) Initial Bit Name Value Description PWRDN0_O Controls power down for DDR in Power Down mode. 0: Not subject to power down 1: Subject to power down R01UH1014EJ0110 Rev.1.10 Page 562 of 3776 Nov 30, 2023...
Page 563 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.240 Power Down MSTOP Register (CPG_PWRDN_MSTOP) It works in conjunction with the Power Down IP register to control the standstill state of the unit in Power Down mode. PWRDN — — — — —...
Page 564 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.241 Power Down CLKON Register (CPG_PWRDN_CLKON) In conjunction with the Power Down IP register, it controls the ON/OFF of each unit clock in Power Down mode. PWRDN — — — — — — —...
Page 565 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.242 Power Down RST Register (CPG_PWRDN_RST) It works in conjunction with the Power Down IP register to control the reset of each unit in Power Down mode. PWRDN — — — — — —...
Page 566 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.243 Return Func 1 Register (CPG_RET_FUNC1) RSTB_ — — — — — — — — — — — — — — — Initial Value R0W1 — — — — — — — — —...
Page 567 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.244 Return Func 2 Register (CPG_RET_FUNC2) — — — — — — — — — — — — — — — — Initial Value — — — — — — — — — —...
Page 568 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.245 Return Func 3 Register (CPG_RET_FUNC3) — — — — — — — — — — — — — — — — Initial Value STATU — — — — — — — — —...
Page 569 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.2.4.246 Other Function Register 2 (CPG_OTHERFUNC2_REG) This register is used for miscellaneous functions. RES15_ RES14_ RES13_ RES12_ RES11_ RES10_ RES9_ RES8_ RES7_ RES6_ RES5_ RES4_ RES3_ RES2_ RES1_ RES0_ ON_WE ON_WE ON_WE ON_WE ON_WE ON_WE ON_WE...
Page 570 RZ/G3S Group 7. Clock Pulse Generator (CPG) Functions of the CPG This section describes the functions of the CPG. 7.3.1 Clock Control The CPG has the following five types of clock control functions. ● PLL control, setting, and monitoring functions ●...
Page 571 RZ/G3S Group 7. Clock Pulse Generator (CPG) Table 7.6 Registers for Controlling the PLL Operating Mode Register Name Abbreviation Function PLLn (SSCG) standby control registers CPG_PLLn_STBY Standby mode setting (reset state) and SSCG (n = 1, 4 or 6) enable or disable setting (2) Output Clock Setting The CPG registers are used to specify the clocks output from the PLL.
Page 572 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.3.1.2 Clock Frequency Dividers and Selectors The CPG uses several frequency dividers and selectors to provide appropriate clocks that meet the specifications of individual modules. The frequency dividers and selectors are classified into the dynamic switching type that can be switched without generating a glitch and the static switching type that should be switched after the clock for the target module is stopped because a glitch is generated if this type of divider or selector is switched while the clock is supplied.
Page 573 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.3.1.4 PLL Clock Monitoring This function monitors whether the PLL1 to PLL4 and PLL6 output clocks are operating. The frequency in the CPG is divided to obtain the frequency that can be monitored through the external pin of this LSI and then output to the upper layer.
Page 574 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.3.2 Clock Generation and Control Functions The following types of reset are provided. Table 7.10 Reset Types Type Method Source Range of Reset System reset Hardware reset Reset by PRST# WDT system reset WDT overflow, etc.
Page 575 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.3.2.1 Range of Reset Application The following shows the application (target) range of the reset generated by each reset source. (1) Hardware sources (PRST#, TRST#, and DEBUGEN) (2) WDT system reset sources Table 7.11 Range of Reset Application Reset Source CST-IF...
Page 576 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.3.2.2 System Reset (External Pin) A system reset is applied when the reset signal from the external PRST# pin is asserted and it initializes the entire LSI. 7.3.2.3 WDT System Reset This LSI has three WDT channels and the CPG issues a reset request when any of the following sources is generated. WDT Channel Target of Monitoring Function...
Page 577 RZ/G3S Group 7. Clock Pulse Generator (CPG) (1) WDT System Reset Circuit The reset requests from three WDT channels can be assigned to the desired signals shown below by using the masking function specified through the settings of the WDTRSTSEL register implemented in the CPG. If a bit in the WDTRSTSEL register is set to 1, the corresponding signal is asserted when the WDT issues a reset request.
Page 578 RZ/G3S Group 7. Clock Pulse Generator (CPG) (2) WDTOVF_PERROUT Signal This is an external signal that notifies the system that the WDT has applied a WDT system reset to this LSI. If another WDT system reset is requested before the output of this signal pulse is completed, it is ignored. The GPIO settings of the WDTOVF_PERROUT# pin such as the driving capability are reset by the GPIO_RST_WDTOVFN signal for the CPG_WDTOVFRST[3:0] register bits.
Page 579 RZ/G3S Group 7. Clock Pulse Generator (CPG) (3) WDT Overflow System Reset Register (CPG_WDTOVF_RST) After the release from the WDT system reset applied by the WDT system reset circuit in response to a reset request such as a WDT overflow, this register is used to identify the WDT channel that generated the reset request. This register is not reset by the WDT system reset generated by the WDT.
Page 580 RZ/G3S Group 7. Clock Pulse Generator (CPG) (4) Timing of Cortex-A55 Cold Reset due to the WDT Source The following figure shows the timing of the cold reset for the Cortex-A55 alone due to the WDT source. WDT Cortex-A55 Single Reset Time Chart OSC CLK Cortex-A55 Core 0 Cause OVF occurrence WDT0_WDTRSTB...
Page 581 RZ/G3S Group 7. Clock Pulse Generator (CPG) (5) Timing of Cortex-M33 Cold Reset due to the WDT Source The following figure shows the timing of the cold reset for the Cortex-M33 alone due to the WDT source.For Cortex- M33_FPU operation, change the signal name etc. from CM33_* to CM33_FPU_*. WDT Cortex-M33 Single Reset Time Chart OSC CLK Cortex-M33 Cause OVF occurrence...
Page 582 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.3.2.4 Cortex-A55 Reset The following four types of reset corresponding to the target ranges of reset are provided for the Cortex-A55. When the P-Channel circuit receives a request for a warm reset ((2), (3) below), the P-Channel control is required before the application of a reset to the Cortex-A55.
Page 583 RZ/G3S Group 7. Clock Pulse Generator (CPG) (a) P-Channel Control Registers in the Cortex-A55 The Cortex-A55 provides a P-Channel for power control for each of the regions — that is, the cluster region including the L3 and SCU, Core 0 region. The P-Channel is driven in the PERIPHCLK domain, and the CPG contains the registers for controlling and monitoring the P-Channel signals other than the PACTIVE signal.
Page 584 RZ/G3S Group 7. Clock Pulse Generator (CPG) Warm Reset Although the CPG has P-Channel control registers, it does not automatically control the P-Channel when a warm reset is requested; the user should control the P-Channel by software. Figure 7.6 shows a flowchart and Figure 7.7 shows a timing chart of the handshake for a warm reset through the Cortex-A55 P-Channel.
Page 585 RZ/G3S Group 7. Clock Pulse Generator (CPG) Warm reset sequence (assert: accepted) Issue warm reset after OFF state transition is granted. P-Channel Handshake. If PACCEPT is returned, the transition is permitted. Warm reset PSTATE PREQ PACCEPT PDENY Warm reset sequence (assert: denied) Handshake on P-Channel.
Page 586 RZ/G3S Group 7. Clock Pulse Generator (CPG) (c) Cortex-A55 Warm Reset Sequence The following describes the warm reset sequence through the P-Channel. Figure 7.8 shows a waveform when a warm reset of Cortex-A55 Core 0 is requested and accepted. When the request is denied, steps 1 to 4 are repeated until the request is accepted.
Page 587 RZ/G3S Group 7. Clock Pulse Generator (CPG) (2) Operation of the Cortex-A55 Reset Control Circuit The reset control circuit asserts the reset signal assigned to the reset request from the reset generator or software. Reset Request Source Reset Signal Assertion Reset Signal Deassertion System reset The CPG asserts the reset signal assigned to...
Page 588 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.3.2.5 Cortex-M33 Reset Two types of reset corresponding to the target ranges of reset are provided for the Cortex-M33. When a request to reset the Cortex-M33 alone is generated in the WDT, an error has probably occurred in the Cortex- M33, and the application of a warm reset may be difficult because the warm reset requires a handshake through the P- Channel.
Page 589 RZ/G3S Group 7. Clock Pulse Generator (CPG) (3) Operation of the Cortex-M33 Reset Control Circuit The reset control circuit asserts the reset signal assigned to the reset request from the reset generator or software. Reset Request Source Reset Signal Assertion Reset Signal Deassertion System reset The software reset register is set to the initial...
Page 590 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.3.2.6 Module Reset Application Control The application of a reset is controlled for individual modules. In addition to a reset applied to individual modules according to register settings by software, some modules are reset in a certain reset mode.
Page 591 RZ/G3S Group 7. Clock Pulse Generator (CPG) Operating Procedures This section describes the procedures for operating the CPG. 7.4.1 Procedures for Supplying and Stopping Module Clocks Use the following procedures to switch between the supply and stop of the target clock for a module. * Sample procedures for the SRAM_MCPU clock (SRAM_MCPU_ACLK0) are described here.
Page 592 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.4.2 Procedures for Supplying and Stopping Reset Signals Use the following procedures to switch between the supply (reset state) and stop (released from the reset state) of the target reset signal for a module. * Sample procedures for the SRAM_MCPU reset (SRAM_MCPU_ARESETN0) are described here.
Page 593 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.4.4 Procedures for PLL Setup The following shows the procedures for PLL setup. 7.4.4.1 Procedure for Setting PLL Normal Mode (Changing the Output Clock and SSCG Mode) Use the following procedure to shift the PLL from the standby mode to the normal mode (change the output clock and SSCG mode).
Page 594 RZ/G3S Group 7. Clock Pulse Generator (CPG) NOTE If there is no change in a parameter in step (2) or (3), the corresponding register does not need to be modified. 7.4.4.2 Procedure for Setting PLL Standby Mode Use the following procedure to shift the PLL from the normal standby mode to the standby mode. [n = 1, 4 or 6: PLL1, PLL4 or PLL6] 1) Setting the PLL standby mode ●...
Page 595 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.4.5 Procedure for Switching the Division Ratio of the Dynamic Switching Frequency Dividers Use the following procedure to set the division ratio of the dynamic switching frequency dividers. * A sample procedure for DIV_PLL1 is described here. 1) Confirming the DIV_PLL1 state (checking that it is not busy) ●...
Page 596 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.4.6 Procedure for Switching Clocks by the Dynamic Switching Frequency Selectors Use the following procedure to switch clocks by the dynamic switching frequency selectors. * A sample procedure for SEL_PLL4 is described here. 1) Confirming the SEL_PLL4 state (checking that it is not busy) ●...
Page 597 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.4.7 Procedure for Switching Clocks by the Static Switching Selectors Use the following procedure to set the division ratio of the static switching frequency dividers and to switch clocks by the static switching frequency selectors. When a source clock is active: Stop the clock.
Page 598 RZ/G3S Group 7. Clock Pulse Generator (CPG) 7.4.10 General Operating Procedures The following describes general operating procedures. 7.4.10.1 Procedure for Writing to Registers The registers in the CPG have write-enable flags in the upper 16 bits and normal data fields in the lower 16 bits except for the registers shown below.
Page 599 RZ/G3S Group 8. Interrupt Controller Interrupt Controller The interrupt controller decides the priority of interrupt sources and controls interrupt requests to the CPU. The interrupt controller registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority.
Page 600 RZ/G3S Group 8. Interrupt Controller 8.1.1 External Signal Pins The following table shows external signal pins for Interrupt Controller. Table 8.1 External Signal Pins Name Width Description NMI (Non Maskable Interrupt) pin. Refer to Section 8.7.1. IRQ0 – IRQ7 IRQ (Interrupt Request) pins. GPIO pins can be used as IRQ pins.
Page 601 RZ/G3S Group 8. Interrupt Controller 8.1.2 Block Diagram The block diagram of Interrupt Controller is as follows. IA55 Cortex-A55 External IRQ0-7 Interrupt SPI0-479 AXI4 P0_0 – Stream GPIO GIC-600 P18_5 PPI0-15 GPIOINT TINT 0-31 0-81 Internal Internal Peripheral IP Peripheral Internal Interrupt Interrupt...
Page 602 RZ/G3S Group 8. Interrupt Controller IM33/IM33_FPU IM33/IM33_FPU performs various interrupt controls including synchronization for the external interrupts of NMI, IRQ and GPIOINT and internal peripheral interrupts output by each IP. And it notifies the interrupt to the built-in interrupt controller (NVIC) for Cortex-M33/Cortex-M33_FPU. Select 32 TINT from 82 GPIOINT.
Page 603 RZ/G3S Group 8. Interrupt Controller Interrupt Mapping The following table indicates interrupt mapping for Cortex-A55 and Cortex-M33/Cortex-M33_FPU. Refer to Section 14, Direct Memory Access Controller with the interrupts through DMA Controller, and Section 8.8.1. Table 8.2 Interrupt Mapping (1/15) Cortex- Cortex- Cortex-A55 M33_FPU...
Page 604 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (2/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note NMI pin SPI 0 IRQ 0 IRQ 0 Level IRQ pins IRQ0 SPI 1...
Page 605 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (3/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note SYSC SYS_LPM_INT SPI 39 IRQ 39 IRQ 39 Level SYS_CA55STBYDONE_INT SPI 40 IRQ 40...
Page 606 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (4/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note MHU for CM33_FPU msg_ch0_ns ― ― ― IRQ 58 Level rsp_ch2_ns ―...
Page 607 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (5/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note DMAC (Secure) DAMERR_S SPI 94 IRQ 94 IRQ 94 Edge DMAINT0_S SPI 95...
Page 608 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (6/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note GPT (Ch0) CCMPA0 SPI 128 IRQ 128 IRQ 128 Edge CCMPB0 SPI 129...
Page 609 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (7/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note GTP (ch3) CCMPA3 SPI 167 IRQ 167 IRQ 167 Edge CCMPB3 SPI 168...
Page 610 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (8/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note GPT (ch6) CCMPA6 SPI 206 IRQ 206 IRQ 206 Edge CCMPB6 SPI 207...
Page 611 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (9/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note SSIF (ch2) INT_ssif_int_req_2 SPI 246 IRQ 246 IRQ 246 Level INT_ssif_dma_rx_2 SPI 247...
Page 612 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (10/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note I2C (ch3) INTRIICTEI3 SPI 281 IRQ 281 IRQ 281 Level INTRIICNAKI3 SPI 282...
Page 613 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (11/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note SCIFA (ch0) ERI0 SPI 320 IRQ 320 IRQ 320 Level BRI0 SPI 321...
Page 614 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (12/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note RSPI (ch1) SPEI1 SPI 361 IRQ 361 IRQ 361 Level SPRI1 SPI 362...
Page 615 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (13/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note PCIe INT_SERR SPI 395 IRQ 395 IRQ 395 Level INT_SERR_COR SPI 396 IRQ 396...
Page 616 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (14/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note GPIO Interrupt TINT0 SPI 429 IRQ 429 IRQ 429 Level TINT1 SPI 430...
Page 617 RZ/G3S Group 8. Interrupt Controller Table 8.2 Interrupt Mapping (15/15) Cortex- Cortex- Cortex-A55 M33_FPU Interrupt SGI, PPI, Interrupt Interrupt Source* Cause of Interrupt SPI No. IRQ No.* IRQ No.* Type* Note Reserved ― SPI 473 IRQ 473 IRQ 473 ― Reserved ―...
Page 618 RZ/G3S Group 8. Interrupt Controller GIC-600 and NVIC Register Configuration  GIC-600 Register Refer to Arm ® CoreLink™ GIC-600 Generic Interrupt Controller Revision: r1p6 Technical Reference Manual. ITS and LPI are not supported. Base Address: H’0_1240_0000 (Cortex-A55 Address Space) Base Address: H’5240_0000 (Cortex-M33/Cortex-M33_FPU Address Space Non-Secure) Base Address: H’4240_0000 (Cortex-M33/Cortex-M33_FPU Address Space Secure) Remark Base address of Non-Secure and Secure are exchangeable by SYS_IPCONT_IDAUZERONS register for...
Page 619 RZ/G3S Group 8. Interrupt Controller IA55 and IM33/IM33_FPU Register Configuration  IA55 Base Address: H’0_1105_0000 (Cortex-A55Address Space) Base Address: H’5105_0000 (Cortex-M33/Cortex-M33_FPU Address Space Non-Secure) Base Address: H’4105_0000 (Cortex-M33/Cortex-M33_FPU Address Space Secure)  IM33 Base Address: H’0_1106_0000 (Cortex-A55 Address Space) Base Address: H’5106_0000 (Cortex-M33/Cortex-M33_FPU Address Space Non-Secure) Base Address: H’4106_0000 (Cortex-M33/Cortex-M33_FPU Address Space Secure) ...
Page 620 RZ/G3S Group 8. Interrupt Controller The following table shows IA55 and IM33/IM33_FPU Register list. Prohibit to write undefined area. Table 8.3 IA55 and IM33/IM33_FPU Register List Access Size Register Name Abbreviation Initial Value Address NMI Status Control Register NSCR H’0000_0000 H’0000 NMI Interrupt Type Selection Register NITSR...
Page 621 RZ/G3S Group 8. Interrupt Controller IA55 and IM33/IM33_FPU Register Descriptions 8.6.1 NMI Status Control Register (NSCR) This register shows NMI status. — — — — — — — — — — — — — — — NSMON Initial Value — —...
Page 622 RZ/G3S Group 8. Interrupt Controller 8.6.2 NMI Interrupt Type Selection Register (NITSR) This register selects NMI detecting method. — — — — — — — — — — — — — — — — Initial Value — — — — —...
Page 623 RZ/G3S Group 8. Interrupt Controller 8.6.3 IRQ Status Control Register (ISCR) This register shows IRQ status. — — — — — — — — — — — — — — — — Initial Value — — — — — — —...
Page 624 RZ/G3S Group 8. Interrupt Controller 8.6.4 IRQ Interrupt Type Selection Register (IITSR) This register selects IRQ detecting method. — — — — — — — — — — — — — — — — Initial Value IITSEL7 IITSEL6 IITSEL5 IITSEL4 IITSEL3 IITSEL2 IITSEL1...
Page 625 RZ/G3S Group 8. Interrupt Controller 8.6.5 TINT Status Control Register (TSCR) This register shows TINT status. TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT Initial Value TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT TSTAT9 TSTAT8 TSTAT7 TSTAT6 TSTAT5 TSTAT4 TSTAT3 TSTAT2 TSTAT1 TSTAT0 Initial Value Initial...
Page 626 RZ/G3S Group 8. Interrupt Controller 8.6.6 TINT Interrupt Type Selection Register0 (TITSR0) This register selects detecting method of TINT15 to TINT0. TITSEL15 TITSEL14 TITSEL13 TITSEL12 TITSEL11 TITSEL10 TITSEL9 TITSEL8 Initial Value TITSEL7 TITSEL6 TITSEL5 TITSEL4 TITSEL3 TITSEL2 TITSEL1 TITSEL0 Initial Value Initial Bit Name Value...
Page 627 RZ/G3S Group 8. Interrupt Controller 8.6.8 TINT Source Selection Register0 (TSSR0) This register selects the interrupt source of TINT3 to TINT0. Refer to Section 8.7.3 about mapping GPIOINT onto GPIO pin. TIEN3 TSSEL3 TIEN2 TSSEL2 Initial Value TIEN1 TSSEL1 TIEN0 TSSEL0 Initial Value Initial...
Page 628 RZ/G3S Group 8. Interrupt Controller 8.6.9 TINT Source Selection Register1 (TSSR1) This register selects the interrupt source of TINT7 to TINT4. Refer to Section 8.7.3 about mapping GPIOINT onto GPIO pin. TIEN7 TSSEL7 TIEN6 TSSEL6 Initial Value TIEN5 TSSEL5 TIEN4 TSSEL4 Initial Value Initial...
Page 629 RZ/G3S Group 8. Interrupt Controller 8.6.10 TINT Source Selection Register2 (TSSR2) This register selects the interrupt source of TINT11 to TINT8. Refer to Section 8.7.3 about mapping GPIOINT onto GPIO pin. TIEN11 TSSEL11 TIEN10 TSSEL10 Initial Value TIEN9 TSSEL9 TIEN8 TSSEL8 Initial Value Initial...
Page 630 RZ/G3S Group 8. Interrupt Controller 8.6.11 TINT Source Selection Register3 (TSSR3) This register selects the interrupt source of TINT15 to TINT12. Refer to Section 8.7.3 about mapping GPIOINT onto GPIO pin. TIEN15 TSSEL15 TIEN14 TSSEL14 Initial Value TIEN13 TSSEL13 TIEN12 TSSEL12 Initial Value Initial...
Page 631 RZ/G3S Group 8. Interrupt Controller 8.6.12 TINT Source Selection Register4 (TSSR4) This register selects the interrupt source of TINT19 to TINT16. Refer to Section 8.7.3 about mapping GPIOINT onto GPIO pin. TIEN19 TSSEL19 TIEN18 TSSEL18 Initial Value TIEN17 TSSEL17 TIEN16 TSSEL16 Initial Value Initial...
Page 632 RZ/G3S Group 8. Interrupt Controller 8.6.13 TINT Source Selection Register5 (TSSR5) This register selects the interrupt source of TINT23 to TINT20. Refer to Section 8.7.3 about mapping GPIOINT onto GPIO pin. TIEN23 TSSEL23 TIEN22 TSSEL22 Initial Value TIEN21 TSSEL21 TIEN20 TSSEL20 Initial Value Initial...
Page 633 RZ/G3S Group 8. Interrupt Controller 8.6.14 TINT Source Selection Register6 (TSSR6) This register selects the interrupt source of TINT27 to TINT24. Refer to Section 8.7.3 about mapping GPIOINT onto GPIO pin. TIEN27 TSSEL27 TIEN26 TSSEL26 Initial Value TIEN25 TSSEL25 TIEN24 TSSEL24 Initial Value Initial...
Page 634 RZ/G3S Group 8. Interrupt Controller 8.6.15 TINT Source Selection Register7 (TSSR7) This register selects the interrupt source of TINT31 to TINT28. Refer to Section 8.7.3 about mapping GPIOINT onto GPIO pin. TIEN31 TSSEL31 TIEN30 TSSEL30 Initial Value TIEN29 TSSEL29 TIEN28 TSSEL28 Initial Value Initial...
Page 635 RZ/G3S Group 8. Interrupt Controller 8.6.16 Bus Error Interrupt Status Control Register0 (BEISR0) This register shows Bus error status. Refer to LSI Internal Bus section and Section 8.7.4.1 for bus error interrupt cause. BESTA BESTA BESTA BESTA BESTA BESTA BESTA BESTA BESTA BESTA...
Page 636 RZ/G3S Group 8. Interrupt Controller 8.6.17 Bus Error Interrupt Status Control Register1 (BEISR1) This register shows Bus error status. Refer to LSI Internal Bus section and Section 8.7.4.1 for bus error interrupt cause. — — — — — — — —...
Page 637 RZ/G3S Group 8. Interrupt Controller 8.6.18 ECCRAM Error Interrupt Status Control Register0 (EREISR0) This register shows ECC 1bit Error status of ECCRAMA0 and ECCRAMA1. Refer to Section 8.7.4.2 for ECCRAM error interrupt cause. — — — — — — — —...
Page 638 RZ/G3S Group 8. Interrupt Controller 8.6.19 ECCRAM Error Interrupt Status Control Register1 (EREISR1) This register shows ECC 1bit Error status of ECCRAMM0 and ECCSRAMM1. Refer to Section 8.7.4.2 for ECCRAM error interrupt cause. — — — — — — — —...
Page 639 RZ/G3S Group 8. Interrupt Controller 8.6.20 ECCRAM Error Interrupt Status Control Register0 (EREISR2) This register shows ECC 2bit Error status of ECCRAMA0 and ECCRAMA1. Refer to Section 8.7.4.2 for ECCRAM error interrupt cause. — — — — — — — —...
Page 640 RZ/G3S Group 8. Interrupt Controller 8.6.21 ECCRAM Error Interrupt Status Control Register1 (EREISR3) This register shows ECC 2bit Error status of ECCRAMM0 and ECCSRAMM1. Refer to Section 8.7.4.2 for ECCRAM error interrupt cause. — — — — — — — —...
Page 641 RZ/G3S Group 8. Interrupt Controller 8.6.22 ECCRAM Error Interrupt Status Control Register0 (EREISR4) This register shows ECC Overflow Error status of ECCRAMA0 and ECCRAMA1. Refer to Section 8.7.4.2 for ECCRAM error interrupt cause. — — — — — — — —...
Page 642 RZ/G3S Group 8. Interrupt Controller 8.6.23 ECCRAM Error Interrupt Status Control Register1 (EREISR5) This register shows ECC Overflow Error status of ECCRAMM0 and ECCSRAMM1. Refer to Section 8.7.4.2 for ECCRAM error interrupt cause. — — — — — — — —...
Page 643 RZ/G3S Group 8. Interrupt Controller 8.6.24 Interrupt Selection (GPT/MTU3a) Register0 (INTPMSEL0) This register selects the GPT interrupts and MTU3a interrupts. Refer to Section 8.7.5 for the interrupt mapping. PMINT PMINT PMINT PMINT PMINT PMINT PMINT PMINT PMINT PMINT PMINT PMINT PMINT PMINT PMINT...
Page 644 RZ/G3S Group 8. Interrupt Controller 8.6.25 Interrupt Selection (GPT/MTU3a) Register1 (INTPMSEL1) This register selects the GPT interrupts and MTU3a interrupts. Refer to Section 8.7.5 for the interrupt mapping. — — — — — — — — — — — — —...
Page 645 RZ/G3S Group 8. Interrupt Controller Operation 8.7.1 NMI Interrupt NMI interrupt is the highest priority interrupt by default even though it can be masked. NMI is not treated as NMI exception. [Setting] A noise filter function of NMI pin can be enabled by GPIO register setting. ●...
Page 646 RZ/G3S Group 8. Interrupt Controller 8.7.3 GPIO Interrupt (TINT) GPIO interrupt is the interrupt using GPIO pins as external interrupt input pins. [Setting] When using GPIO pins as interrupts, assign GPIO pins as external interrupt input pins (GPIOINT0-81) by GPIO ●...
Page 647 RZ/G3S Group 8. Interrupt Controller Table 8.4 GPIOINT Mapping GPIO Pin GPIOINT GPIO Pin GPIOINT P0_0 GPIOINT0 P8_3 GPIOINT41 P0_1 GPIOINT1 P8_4 GPIOINT42 P0_2 GPIOINT2 P9_0 GPIOINT43 P0_3 GPIOINT3 P9_1 GPIOINT44 P1_0 GPIOINT4 P9_2 GPIOINT45 P1_1 GPIOINT5 P9_3 GPIOINT46 P1_2 GPIOINT6 P10_0 GPIOINT47...
Page 648 RZ/G3S Group 8. Interrupt Controller 8.7.4 Internal Interrupt 8.7.4.1 Bus Error Interrupt Bus error interrupts (BUSERR_INT0-46) generated by system bus are integrated into one interrupt (BUS_ERR_INT) by IA55/IM33/IM33_FPU and the integrated interrupt is notified to CPU. [Status Control] ● Bus error interrupt requests can be confirmed by reading BUS Error Interrupt Status Control Register (BEISR0/1) in IA55/IM33/IM33_FPU.
Page 649 RZ/G3S Group 8. Interrupt Controller Table 8.5 BEISR0 Bus Error Mapping BEISR0 Interrupt Description BESTAT0 BUSERR_INT0 Bus Write Error Interrupt for CA55 BESTAT1 BUSERR_INT1 Bus Read Error Interrupt for CA55 BESTAT2 BUSERR_INT2 Bus Write Error Interrupt for CM33_FPU_S BESTAT3 BUSERR_INT3 Bus Read Error Interrupt for CM33_FPU_S BESTAT4 BUSERR_INT4...
Page 650 RZ/G3S Group 8. Interrupt Controller Table 8.6 BEISR1 Bus Error Mapping BEISR1 Interrupt Description BESTAT32 BUSERR_INT32 Bus Read Error Interrupt for CST_AP BESTAT33 BUSERR_INT33 Bus Write Error Interrupt for CM33_S BESTAT34 BUSERR_INT34 Bus Read Error Interrupt for CM33_S BESTAT35 BUSERR_INT35 Bus Write Error Interrupt for CM33_C BESTAT36 BUSERR_INT36...
Page 651 RZ/G3S Group 8. Interrupt Controller 8.7.4.2 ECCRAM Error Interrupt ECCRAM error interrupts generated by On-Chip RAM (ECCRAMA0, ECCRAMA1, ECCRAMM0, ECCRAMM1) are integrated with IA55/IM33/IM33_FPU for each interrupt cause and notified to the CPU. Each On-Chip RAM outputs eight 1-bit ECC error interrupts, eight 2-bit ECC error interrupts and eight overflow error interrupts.
Page 652 RZ/G3S Group 8. Interrupt Controller Table 8.7 ECC 1bit Error Mapping Integrated Register Name Register Status Bit Interrupt Description Interrupt EREISR0 A01ESTAT0 ECCRAMA0_1E0 ECC 1bit Error interrupt bit[31:0] EC7TIE1 A01ESTAT1 ECCRAMA0_1E1 ECC 1bit Error interrupt bit[63:32] A01ESTAT2 ECCRAMA0_1E2 ECC 1bit Error interrupt bit[95:64] A01ESTAT3 ECCRAMA0_1E3 ECC 1bit Error interrupt bit[127:96]...
Page 653 RZ/G3S Group 8. Interrupt Controller Table 8.8 ECC 2bit Error Mapping Integrated Register Name Register Status Bit Interrupt Description Interrupt EREISR2 A02ESTAT0 ECCRAMA0_2E0 ECC 2bit Error interrupt bit[31:0] EC7TIE2 A02ESTAT1 ECCRAMA0_2E1 ECC 2bit Error interrupt bit[63:32] A02ESTAT2 ECCRAMA0_2E2 ECC 2bit Error interrupt bit[95:64] A02ESTAT3 ECCRAMA0_2E3 ECC 2bit Error interrupt bit[127:96]...
Page 654 RZ/G3S Group 8. Interrupt Controller Table 8.9 ECC Overflow Error Mapping Integrated Register Name Register Status Bit Interrupt Description Interrupt EREISR4 A0OFSTAT0 ECCRAMA0_OF0 ECC Overflow Error interrupt bit[31:0] EC7TIOVF A0OFSTAT1 ECCRAMA0_OF1 ECC Overflow Error interrupt bit[63:32] A0OFSTAT2 ECCRAMA0_OF2 ECC Overflow Error interrupt bit[95:64] A0OFSTAT3 ECCRAMA0_OF3 ECC Overflow Error interrupt bit[127:96]...
Page 655 RZ/G3S Group 8. Interrupt Controller 8.7.5 GPT/MTU3a Interrupt Selection GPT interrupt and MTU3a Interrupt are selected by the INTPMSEL0/1 register. Refer to the following tables. Table 8.10 Selection of GPT Interrupt and MTU3a Interrupt by the INTPMSEL0 Register Interrupt Source Cause of Interrupt Interrupt Source Cause of Interrupt...
Page 656 RZ/G3S Group 8. Interrupt Controller Table 8.11 Selection of GPT Interrupt and MTU3a Interrupt by the INTPMSEL1 Register Interrupt Source Cause of Interrupt Interrupt Source Cause of Interrupt Selection Register SPI / IRQ No. GPT (ch5) ADTRGA5 MTU3a (ch6) TCIV6 INTPMSEL1[0] ADTRGB5 MTU3a (ch7)
Page 657 RZ/G3S Group 8. Interrupt Controller Usage Note 8.8.1 Precaution when use the peripheral modules which can initiate DMA Controller Some on-chip peripheral modules use the same signal both for an interrupt request and for a DMA transfer request. Refer to Section 14.4, DMA Extension Resource Selectors 0/0S to 7/7S for detail. If such a module is selected by a DMARSn/nS register, the signal works as a DMA transfer request signal and interrupt requests to the interrupt controller are masked.
Page 658 RZ/G3S Group 9. DDR4/LPDDR4 SDRAM Memory Controller (MEMC) DDR4/LPDDR4 SDRAM Memory Controller (MEMC) DDR4/LPDDR4 SDRAM Memory Controller (MEMC) is External Bus Controller for DDR4/LPDDR4 SDRAM (DDR). This block supports up to DDR4/LPDDR4-1600 SDRAM. Interface bus width is 16 bits. In line ECC can be supported.
Page 659 RZ/G3S Group 9. DDR4/LPDDR4 SDRAM Memory Controller (MEMC) Block Diagram Figure 9.1 shows the diagrams of this unit. SYSC (reg) rst_n ddr_clk AXI4 AXI4 (port 0) (port 1) controller int AXI4 MC (Memory Controller) sref_error (reg) dwc_ddrphy_int_n PHY (DDRPHY_WRAP) PHYTOP (dfi_top_wrapper) APB3 Addr/Ctrl PHY Data PHY...
Page 660 RZ/G3S Group 9. DDR4/LPDDR4 SDRAM Memory Controller (MEMC) [LPDDR4] Not supported followings; ● Interleaving − Gear-down Mode − Fine Granularity Refresh Mode except Normal mode (Fixed 1x) − − − CA Parity R01UH1014EJ0110 Rev.1.10 Page 660 of 3776 Nov 30, 2023...
Page 661 RZ/G3S Group 9. DDR4/LPDDR4 SDRAM Memory Controller (MEMC) Interface 9.3.1 Power, Ground Table 9.2 shows the power and ground pins of this unit. Table 9.2 Power, Ground Name Description DDR_VDDQ Supply Power supply for I/O DDR_VAA Supply Power Supply for PLL Supply Power supply for DDR Core Ground...
Page 662 RZ/G3S Group 9. DDR4/LPDDR4 SDRAM Memory Controller (MEMC) Table 9.3 External Pins List (2/2) Default Function Pin Name Description DDR4 LPDDR4 BP_A31 DRAM Command/Address ― BP_A33 DRAM Command/Address CAS_N ― BP_A34 DRAM Command/Address WE_N ― BP_A35 DRAM Command/Address RAS_N ― BP_A36 DRAM Command/Address ODT0...
Page 663 RZ/G3S Group 9. DDR4/LPDDR4 SDRAM Memory Controller (MEMC) Usage Note 9.4.1 Power On The power on sequence for the DDR_VDDQ and VDD domains is such that either the 2 voltages should be ramped up together or VDD should be ramped up prior to DDR_VDDQ in order to prevent voltage stress in the DDR IOs. R01UH1014EJ0110 Rev.1.10 Page 663 of 3776...
Page 664 RZ/G3S Group 10. On-chip RAM 10. On-chip RAM This LSI has an on-chip RAM for work area. These memory units can be used to store instructions or data. The operation and write access to the on-chip RAM can be enabled or disabled through the RAM enable bit ((VCEN in SYS_RAMn_EN register) (n = 0-3) and RAM write enable bit (VLWEN in SYS_RAMn_EN register) (n = 0-3).
Page 665 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM 11. Error Correcting Code (ECC) for On-Chip RAM 11.1 Overview This LSI chip has four 256-Kbyte areas of on-chip RAM for use as the working area. Each of on-chip RAM incorporates an ECC function, which allows the detection and correction of 1-bit errors and the detection of 2-bit errors.
Page 666 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM 11.2 Register Configuration Table 11.1 and Table 11.2 respectively show the base register and base address. The addresses of the ECC registers are represented by offsets from the base address. Table 11.1 Base Register Base Register Name...
Page 667 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM Table 11.3 lists the ECC registers. Do not attempt access to the on-chip RAM areas while the registers listed in Table 11.3 are being set. Table 11.3 List of the ECC Registers (1/2) Access Size Channel...
Page 668 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM Table 11.3 List of the ECC Registers (2/2) Access Channel Register Name Abbreviation Initial Value Address Size ECC control register_4 <REG_base>CTL_4 H’0000_0010 <ADR_base> + H’0100 ECC error address register 0_4 <REG_base>EAD0_4 H’0000_0000 <ADR_base>...
Page 669 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM 11.3 Register Descriptions 11.3.1 ECC Control Registers_n (<REG_base>CTL_n) (n = 0 to 7) Each ECC control register_n is used to control the ECC function in the corresponding channel n shown in Figure 11.1. After writing the initial value to the entire usage area of the on-chip RAM, set the given ECERVF bits to 1 to enable error detection.
Page 670 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM Initial Bit Name Value Description ECOVFF ECC Overflow Detection Flag This bit is set to 1 and an overflow interrupt is output on detection of an error when the ECC error address registers (<REG_base>EADm_n (m = 0 to 7)) all contain data. An overflow interrupt is output even if the error is detected while the setting of this bit is already 1.
Page 671 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM Initial Bit Name Value Description — Reserved When read, the initial value is read. When writing, be sure to write the initial value. Operation is not guaranteed if a value other than the initial value is written. R01UH1014EJ0110 Rev.1.10 Page 671 of 3776...
Page 672 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM 11.3.2 ECC Error Address Registers m_n (<REG_base>EADm_n) (m = 0 to 7) (n = 0 to 7) When a 1- or 2-bit error occurs, up to eight error addresses are sequentially stored in the registers from <REG_base>EAD0_n to <REG_base>EAD7_n.
Page 673 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM 11.4 Initializing the ECC Function Initialize the ECC by following the procedure below to enable the ECC function. Set the VECCEN bit in the ECCRAM setting register corresponding to the RAM area for which the ECC function is to be enabled to 1.
Page 674 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM 11.6 Usage Notes 11.6.1 Notes on Setting the Registers of This Module Ensure that none of the bus masters proceeds with access to the on-chip RAM areas while the registers listed in Table 11.3 are being set up.
Page 675 RZ/G3S Group 11. Error Correcting Code (ECC) for On-Chip RAM 11.6.4 ECC Error Address Register Overwrite Conditions If a new ECC error occurs with the ECC error address stored up to <REG_base> EAD7_n, <REG_base> EAD7_n may or may not be overwritten. The conditions to be overwritten are shown below. Error Address Storage Status Up to <REG_base>EAD7_n <REG_base>...
Page 676 RZ/G3S Group 12. Message Handling Unit (MHU) 12. Message Handling Unit (MHU) MHU is a function for message communication between Cortex-A55(CA55) cores and Cortex- M33(CM33/CM33_FPU). Message communication is done by shared RAM (On-chip RAM) for passing message and response between CPUs and the function (MHU) for notifying when messages and responses are stored in the memory. 12.1 Features Table 12.1 shows MHU feature summary.
Page 677 RZ/G3S Group 12. Message Handling Unit (MHU) Message/response interrupt control pclk Channel Sn (Message/response send) n = 0 - 5 Channel NSn (Message/response send) n = 0 - 5 presetn Message send control Set register Status register clear Clear register Address APB Slave IF Message/...
Page 678 RZ/G3S Group 12. Message Handling Unit (MHU) Message/response interrupt control registers Registers that control message/response interrupts. The message/response interrupt control register controls interrupts with the set register, clear register, and status register. An interrupt is asserted by writing “1” to the set register. The interrupt is negated by writing “1” to the clear register.
Page 679 RZ/G3S Group 12. Message Handling Unit (MHU) Event routing control circuit Figure 12.2 figure shows event routing control circuit. In detail, refer to Section 12.5.2, Event Routing Function. CA55 CM33_FPU CM33 MHU_ERU_BS MHU_ERU_BM MHU_ERU_BS MHU_ERU_BM MHU_ERU_BS MHU_ERU_BM (u_BS) (u_BM) (u_BS) (u_BM) (u_BS) (u_BM)
Page 680 RZ/G3S Group 12. Message Handling Unit (MHU) 12.2 Interrupt Table 12.3 shows interrupt output. Table 12.3 Interrupt Type Output Description Pulse/Level Active Level msg_ch0_ns Non-secure message transmission interrupt (CA55 -> CM33_FPU) Level HIGH rsp_ch0_ns Non-secure response transmission interrupt (CM33_FPU -> CA55) Level HIGH msg_ch1_ns...
Page 681 RZ/G3S Group 12. Message Handling Unit (MHU) 12.3 Register Configuration Table 12.4 shows address mapping for MHU. MHU has 4KB address space. Table 12.4 MHU Address Map Offset Address (CA55 MHU Base address: H’0_1040_0000) (CM33/CM33_FPU Secure MHU Base address: H’4040_0000) (CM33/CM33_FPU Non-secure MHU Base address: H’5040_0000) Description H’0000 –...
Page 682 RZ/G3S Group 12. Message Handling Unit (MHU) Table 12.6 shows registers Table 12.6 List of Registers (1/4) Offset Address Register Name Abbreviation Initial value Access Size Non-secure message/response interrupt Non-secure message transmission interrupt register (CA55 -> CM33_FPU) channel 0 H’0000 message transmission interrupt Status register MSG_INT_STS0_NS H’0000_0000...
Page 683 RZ/G3S Group 12. Message Handling Unit (MHU) Table 12.6 List of Registers (2/4) Offset Address Register Name Abbreviation Initial value Access Size Non-secure message transmission interrupt register (CM33 -> CA55) channel 4 H’0080 message transmission interrupt Status register MSG_INT_STS4_NS H’0000_0000 32 bits H’0084 message transmission interrupt Set register...
Page 684 RZ/G3S Group 12. Message Handling Unit (MHU) Table 12.6 List of Registers (3/4) Offset Address Register Name Abbreviation Initial value Access Size H’084C Reserved — — — Non-secure software interrupt register channel 5 H’0850 software interrupt Status register SW_INT_STS5_NS H’0000_0000 32 bits H’0854 software interrupt Set register...
Page 685 RZ/G3S Group 12. Message Handling Unit (MHU) Table 12.6 List of Registers (4/4) Offset Address Register Name Abbreviation Initial value Access Size H’1078 response transmission interrupt Clear register RSP_INT_CLR3_S H’0000_0000 32 bits H’107C Reserved — — — Secure message transmission interrupt register (CM33 -> CA55) channel 4 H’1080 message transmission interrupt Status register MSG_INT_STS4_S...
Page 686 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4 Register Descriptions 12.4.1 Non-Secure Message Transmission Interrupt Status Register (CA55 -> CM33_FPU) 12.4.2 Non-Secure Message Transmission Interrupt Status Register (CA55 -> CM33) 12.4.3 Non-Secure Message Transmission Interrupt Status Register (CM33_FPU - > CA55) 12.4.4 Non-Secure Message Transmission Interrupt Status Register (CM33_FPU - >...
Page 687 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.7 Non-Secure Message Transmission Interrupt Set Register (CA55 -> CM33_FPU) 12.4.8 Non-Secure Message Transmission Interrupt Set Register (CA55 -> CM33) 12.4.9 Non-Secure Message Transmission Interrupt Set Register (CM33_FPU -> CA55) 12.4.10 Non-Secure Message Transmission Interrupt Set Register (CM33_FPU -> CM33) 12.4.11 Non-Secure Message Transmission Interrupt Set Register (CM33 ->...
Page 688 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.13 Non-Secure Message Transmission Interrupt Clear Register (CA55 -> CM33_FPU) 12.4.14 Non-Secure Message Transmission Interrupt Clear Register (CA55 -> CM33) 12.4.15 Non-Secure Message Transmission Interrupt Clear Register (CM33_FPU -> CA55) 12.4.16 Non-Secure Message Transmission Interrupt Clear Register (CM33_FPU -> CM33) 12.4.17 Non-Secure Message Transmission Interrupt Clear Register (CM33 ->...
Page 689 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.19 Non-Secure Response Transmission Interrupt Status Register (CM33_FPU - > CA55) 12.4.20 Non-Secure Response Transmission Interrupt Status Register (CM33 -> CA55) 12.4.21 Non-Secure Response Transmission Interrupt Status Register (CA55 -> CM33_FPU) 12.4.22 Non-Secure Response Transmission Interrupt Status Register (CM33 -> CM33_FPU) 12.4.23 Non-Secure Response Transmission Interrupt Status Register (CA55 ->...
Page 690 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.25 Non-Secure Response Transmission Interrupt Set Register (CM33_FPU -> CA55) 12.4.26 Non-Secure Response Transmission Interrupt Set Register (CM33 -> CA55) 12.4.27 Non-Secure Response Transmission Interrupt Set Register (CA55 -> CM33_FPU) 12.4.28 Non-Secure Response Transmission Interrupt Set Register (CM33 -> CM33_FPU) 12.4.29 Non-Secure Response Transmission Interrupt Set Register (CA55 ->...
Page 691 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.31 Non-Secure Response Transmission Interrupt Clear Register (CM33_FPU - > CA55) 12.4.32 Non-Secure Response Transmission Interrupt Clear Register (CM33 -> CA55) 12.4.33 Non-Secure Response Transmission Interrupt Clear Register (CA55 -> CM33_FPU) 12.4.34 Non-Secure Response Transmission Interrupt Clear Register (CM33 -> CM33_FPU) 12.4.35 Non-Secure Response Transmission Interrupt Clear Register (CA55 ->...
Page 692 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.37 Non-Secure Software Interrupt Status Register (ch0) 12.4.38 Non-Secure Software Interrupt Status Register (ch1) 12.4.39 Non-Secure Software Interrupt Status Register (ch2) 12.4.40 Non-Secure Software Interrupt Status Register (ch3) 12.4.41 Non-Secure Software Interrupt Status Register (ch4) 12.4.42 Non-Secure Software Interrupt Status Register (ch5) Status register of Non-secure software interrupt Status register (Name: SW_INT_STSn_NS <n=0 to 5>) Access Size:...
Page 693 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.43 Non-Secure Software Interrupt Set Register (ch0) 12.4.44 Non-Secure Software Interrupt Set Register (ch1) 12.4.45 Non-Secure Software Interrupt Set Register (ch2) 12.4.46 Non-Secure Software Interrupt Set Register (ch3) 12.4.47 Non-Secure Software Interrupt Set Register (ch4) 12.4.48 Non-Secure Software Interrupt Set Register (ch5) Set register of Non-secure software interrupt (Name: SW_INT_SETn_NS <n=0 to 5>) Access Size:...
Page 694 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.49 Non-Secure Software Interrupt Clear Register (ch0) 12.4.50 Non-Secure Software Interrupt Clear Register (ch1) 12.4.51 Non-Secure Software Interrupt Clear Register (ch2) 12.4.52 Non-Secure Software Interrupt Clear Register (ch3) 12.4.53 Non-Secure Software Interrupt Clear Register (ch4) 12.4.54 Non-Secure Software Interrupt Clear Register (ch5) Clear register of Non-secure software interrupt Clear register(Name: SW_INT_CLRn_NS <n=0 to 5>) Access Size:...
Page 695 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.55 Secure Message Transmission Interrupt Status Register (CA55 -> CM33_FPU) 12.4.56 Secure Message Transmission Interrupt Status Register (CA55 -> CM33) 12.4.57 Secure Message Transmission Interrupt Status Register (CM33_FPU -> CA55) 12.4.58 Secure Message Transmission Interrupt Status Register (CM33_FPU -> CM33) 12.4.59 Secure Message Transmission Interrupt Status Register (CM33 ->...
Page 696 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.61 Secure Message Transmission Interrupt Set Register (CA55 -> CM33_FPU) 12.4.62 Secure Message Transmission Interrupt Set Register (CA55 -> CM33) 12.4.63 Secure Message Transmission Interrupt Set Register (CM33_FPU -> CA55) 12.4.64 Secure Message Transmission Interrupt Set Register (CM33_FPU -> CM33) 12.4.65 Secure Message Transmission Interrupt Set Register (CM33 ->...
Page 697 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.67 Secure Message Transmission Interrupt Clear Register (CA55 -> CM33_FPU) 12.4.68 Secure Message Transmission Interrupt Clear Register (CA55 -> CM33) 12.4.69 Secure Message Transmission Interrupt Clear Register (CM33_FPU -> CA55) 12.4.70 Secure Message Transmission Interrupt Clear Register (CM33_FPU -> CM33) 12.4.71 Secure Message Transmission Interrupt Clear Register (CM33 ->...
Page 698 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.73 Secure Response Transmission Interrupt Status Register (CM33_FPU -> CA55) 12.4.74 Secure Response Transmission Interrupt Status Register (CM33 -> CA55) 12.4.75 Secure Response Transmission Interrupt Status Register (CA55 -> CM33_FPU) 12.4.76 Secure Response Transmission Interrupt Status Register (CM33 -> CM33_FPU) 12.4.77 Secure Response Transmission Interrupt Status Register (CA55 ->...
Page 699 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.79 Secure Response Transmission Interrupt Set Register (CM33_FPU -> CA55) 12.4.80 Secure Response Transmission Interrupt Set Register (CM33 -> CA55) 12.4.81 Secure Response Transmission Interrupt Set Register (CA55 -> CM33_FPU) 12.4.82 Secure Response Transmission Interrupt Set Register (CM33 -> CM33_FPU) 12.4.83 Secure Response Transmission Interrupt Set Register (CA55 ->...
Page 700 RZ/G3S Group 12. Message Handling Unit (MHU) 12.4.85 Secure Response Transmission Interrupt Clear Register (CM33_FPU -> CA55) 12.4.86 Secure Response Transmission Interrupt Clear Register (CM33 -> CA55) 12.4.87 Secure Response Transmission Interrupt Clear Register (CA55 -> CM33_FPU) 12.4.88 Secure Response Transmission Interrupt Clear Register (CM33 -> CM33_FPU) 12.4.89 Secure Response Transmission Interrupt Clear Register (CA55 ->...
Page 701 RZ/G3S Group 12. Message Handling Unit (MHU) 12.5 Function Description 12.5.1 Inter CPU Communication The hardware configuration is shown in Figure 12.3. Inter-CPU communication is established by sending a message from the message source to the message destination and sending a response from the message destination to the message source.
Page 702 RZ/G3S Group 12. Message Handling Unit (MHU) Table 12.7 Channel and Message Destination/Source Reference Channel Source Destination Message Transmit Register Response Transmit Register channel 0 NS CA55 CM33_FPU MSG_INT_(SET/CLR/STS)0_NS RSP_INT_(SET/CLR/STS)0_NS channel 1 NS CA55 CM33 MSG_INT_(SET/CLR/STS)1_NS RSP_INT_(SET/CLR/STS)1_NS channel 2 NS CM33_FPU CA55 MSG_INT_(SET/CLR/STS)2_NS...
Page 703 RZ/G3S Group 12. Message Handling Unit (MHU) 12.5.2 Event Routing Function (1) 4-Phase handshake Figure 12.4 shows each EVENT I/O interface on the router meets the requirements for a REQ/ACK 4-phase handshake. EVENT I/O interface is considered to be in the Idle state when both REQ/ACK are Low, and in the Busy state during the rest of the period.
Page 704 RZ/G3S Group 12. Message Handling Unit (MHU) (2) Single Event handshake Figure 12.5 is the simplest single event example. A pair of red arrows indicates the start and end of a single REQ/ACK handshake. One EM (Event Master) sends an event to one or more ESs (Event Slave) through an EB (Event Bridge), that is a MHU_ERU.
Page 705 RZ/G3S Group 12. Message Handling Unit (MHU) (3) Multiple Event handshake (Event Hold) If the EVENTO interface is busy and the EVENTI interface receives an event, the EVENTI interface completes the handshake without waiting for the EVENTO interface handshake to complete. EVENTO interface holds the next event until the first event completes.
Page 706 RZ/G3S Group 12. Message Handling Unit (MHU) (4) Multiple Event (Event Integration) If the router has multiple pending events, unified them when the EVENTO interface goes into the Idle state. Event is pending Event is pending Busy Integrated EVENT Figure 12.7 Multiple Event Handshake (EVENT Integration) R01UH1014EJ0110 Rev.1.10...
Page 707 RZ/G3S Group 12. Message Handling Unit (MHU) 12.6 Operation Sequence 12.6.1 Message Transmit Sequence Show Message transmit sequence from Cortex-M33/Cortex-M33_FPU to Cortex-A55 in below and Figure 12.8. Response transmit Message transmit interrupt interrupt CM33/CM33_FPU NVIC CA55 GIC CM33/CM33_FPU CA55 System Bus Response transmit Message transmit Shared RAM...
Page 708 RZ/G3S Group 12. Message Handling Unit (MHU) 12.6.2 Response Transmit Sequence Show Response transmit sequence from Cortex-A55 to Cortex-M33/Cortex-M33_FPU in below and Figure 12.9. Response transmit Message transmit interrupt interrupt CM33/CM33_FPU NVIC CA55 GIC CM33/CM33_FPU CA55 System Bus Response transmit Message transmit Shared RAM Message &...
Page 709 RZ/G3S Group 13. TrustZone Address Space Controller (TZC) 13. TrustZone Address Space Controller (TZC) 13.1 Overview This LSI has six TrustZone Address Space Controller (TZC) to realize memory access in a safe area. It performs security checks on transactions to memory or peripherals. Transactions must meet security requirements to access memory or peripherals.
Page 710 RZ/G3S Group 13. TrustZone Address Space Controller (TZC) 13.1.2 Block Diagram Figure 13.1 shows a block diagram. TZC_SRAM_ACPU1 Interrupt TZC_SRAM_ACPU0 TZC_SRAM_ACPU1_INT Control unit Slave TZC_SRAM_ACPU0_INT interface ACE-Lite Internal Internal Filter unit 0 ACPU ACE-Lite Slave Master RAM for RAM for interface interface ACPU...
Page 711 RZ/G3S Group 13. TrustZone Address Space Controller (TZC) Filter units perform security checks. Each filter unit has an ACE-Lite slave interface and an ACE-Lite master interface. All filter units operate from one set of shared region configuration registers. This ensures consistency across all filter units.
Page 712 RZ/G3S Group 13. TrustZone Address Space Controller (TZC) 13.2 Register Configuration The base address of the TZC associated with each module is as follows: ● TZC_SRAM_ACPU0: Internal RAM for ACPU0 (256KB) H’0_1120_0000 (Cortex-A55 Address Space) H’4120_0000 (Cortex-M33/Cortex-M33_FPU Address Space Secure) H’5120_0000 (Cortex-M33/Cortex-M33_FPU Address Space Non-Secure) TZC_SRAM_ACPU1: Internal RAM for ACPU1 (256KB) ●...
Page 713 RZ/G3S Group 13. TrustZone Address Space Controller (TZC) 13.3 Register Descriptions For details on the functions of TZC-400, see the relevant Technical Reference Manual. (ARM ® CoreLink™ TZC-400 TrustZone ® Address Space Controller Technical Reference Manual, Revision: r0p1) TZC has registers to specify the address area where access is controlled. Please refer Overall Address Space (Table 5.1, Detailed Address Space) for the addresses specified in these registers.
Page 714 RZ/G3S Group 14. Direct Memory Access Controller 14. Direct Memory Access Controller The direct memory access controller can be used in place of the CPU to perform high-speed transfers between external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. This module has controllers that handles secure and non-secure access.
Page 715 RZ/G3S Group 14. Direct Memory Access Controller 14.3 Register Configuration The register configuration is shown in the figure below. Channel Next Register Set Current Register Set Next0 Register Set Source Address 2. Transfer Destination Address Source Address 1. Load Transaction Byte Destination Address Transaction Byte Channel Register Set...
Page 716 RZ/G3S Group 14. Direct Memory Access Controller (b) Current Register Set This register set indicates the source address, destination address, and transfer byte count of the currently executed DMA transaction. The values are loaded from the Next0/1 register set (register mode) or from the descriptor read data (link mode). The user cannot write directly to this register set.
Page 717 RZ/G3S Group 14. Direct Memory Access Controller 14.4 Register Descriptions Table 14.1 lists the register configuration. There are eleven control registers and five status registers for each channel, and twelve common control registers are used by all channels. In addition, there is one extension resource selector per two channels.
Page 718 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (2/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size <Base_NS0> <Base_S0>+ Channel Interval Register 0/0S CHITVL_0 CHITVL_0S H’0000_0000 +H’0030 H’0030 Channel Extension Register 0/0S CHEXT_0 CHEXT_0S H’0000_0000...
Page 719 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (3/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size <Base_NS0> <Base_S0>+ Current Source Address Register 2/2S CRSA_2 CRSA_2S H’0000_0000 +H’0098 H’0098 Current Destination Address Register CRDA_2 CRDA_2S H’0000_0000...
Page 720 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (4/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size <Base_NS0> <Base_S0>+ Next0 Source Address Register 4/4S N0SA_4 N0SA_4S H’0000_0000 +H’0100 H’0100 Next0 Destination Address Register N0DA_4 N0DA_4S H’0000_0000...
Page 721 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (5/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size <Base_NS0> <Base_S0>+ Channel Control Register 5/5S CHCTRL_5 CHCTRL_5S H’0000_0000 +H’0168 H’0168 Channel Configuration Register 5/5S CHCFG_5 CHCFG_5S H’0000_0000...
Page 722 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (6/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size <Base_NS0> <Base_S0>+ Next0 Source Address Register 7/7S N0SA_7 N0SA_7S H’0000_0000 +H’01C0 H’01C0 Next0 Destination Address Register N0DA_7 N0DA_7S H’0000_0000...
Page 723 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (7/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size <Base_NS0> <Base_S0>+ Next0 Source Address Register 8/8S N0SA_8 N0SA_8S H’0000_0000 +H’0400 H’0400 Next0 Destination Address Register N0DA_8 N0DA_8S H’0000_0000...
Page 724 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (8/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size <Base_NS0> <Base_S0>+ Channel Control Register 9/9S CHCTRL_9 CHCTRL_9S H’0000_0000 +H’0468 H’0468 Channel Configuration Register 9/9S CHCFG_9 CHCFG_9S H’0000_0000...
Page 725 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (9/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size Next0 Source Address Register <Base_NS0> <Base_S0>+ N0SA_11 N0SA_11S H’0000_0000 11/11S +H’04C0 H’04C0 Next0 Destination Address Register N0DA_11 N0DA_11S H’0000_0000...
Page 726 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (10/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size <Base_NS0> <Base_S0>+ Channel Control Register 12/12S CHCTRL_12 CHCTRL_12S RW H’0000_0000 +H’0528 H’0528 Channel Configuration Register CHCFG_12 CHCFG_12S H’0000_0000...
Page 727 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (11/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size Next0 Source Address Register <Base_NS0> <Base_S0>+ N0SA_14 N0SA_14S H’0000_0000 14/14S +H’0580 H’0580 Next0 Destination Address Register N0DA_14 N0DA_14S H’0000_0000...
Page 728 RZ/G3S Group 14. Direct Memory Access Controller Table 14.1 Register Configuration (12/12) Abbreviation Address Access Channel Register Name Non-secure Secure Initial Value Non-secure Secure Size <Base_NS0> <Base_S0>+ Channel Control Register 15/15S CHCTRL_15 CHCTRL_15S RW H’0000_0000 +H’05E8 H’05E8 Channel Configuration Register CHCFG_15 CHCFG_15S H’0000_0000...
Page 729 RZ/G3S Group 14. Direct Memory Access Controller (2) APB I/F Base Address Name Base Address <Base_S1> H’0_1181_0000 (Cortex-A55 Address Space) H’4181_0000 (Cortex-M33/Cortex-M33_FPU Address Space Secure) H’5181_0000 (Cortex-M33/Cortex-M33_FPU Address Space Non-Secure) <Base_NS1> H’0_1183_0000 (Cortex-A55 Address Space) H’4183_0000 (Cortex-M33/Cortex-M33_FPU Address Space Secure) H’5183_0000 (Cortex-M33/Cortex-M33_FPU Address Space Non-Secure) Note: Base address of Non-Secure and Secure are exchangeable by SYS_IPCONT_IDAUZERONS register for Cortex-M33 Address...
Page 730 RZ/G3S Group 14. Direct Memory Access Controller 14.4.1 Next Source Address Register n/nS (N0SA_n/nS, N1SA_n/nS) This register sets the DMA transfer source address (32 bits) of DMA channel n (n = 0 to 15) which is to be executed next. N0SA_n/nS is for the Next0 Register Set, and N1SA_n/nS is for the Next1 Register Set. In register mode, set this register set by using software.
Page 731 RZ/G3S Group 14. Direct Memory Access Controller 14.4.3 Next Transaction Byte Register n/nS (N0TB_n/nS, N1TB_n/nS) This register sets the total transfer byte count (DMA transaction) of DMA channel (n = 0 to 15) which is to be executed next. N0TB_n/nS is for the Next0 Register Set, and N1TB_n/nS is for the Next1 Register Set. In register mode, set this register set by using software.
Page 732 RZ/G3S Group 14. Direct Memory Access Controller 14.4.4 Current Source Address Register n/nS (CRSA_n/nS) This register indicates the DMA transfer source address of DMA channel n (n = 0 to 15). The values are loaded from the Next0/1 register set in register mode or from the descriptor read data in link mode. This register cannot be written by software.
Page 733 RZ/G3S Group 14. Direct Memory Access Controller 14.4.5 Current Destination Address Register n/nS (CRDA_n/nS) This register indicates the DMA transfer destination address of DMA channel n (n = 0 to 15). The values are loaded from the Next0/1 register set in register mode or from the descriptor read data in link mode. This register cannot be written by software.
Page 734 RZ/G3S Group 14. Direct Memory Access Controller 14.4.6 Current Transaction Byte Register n/nS (CRTB_n/nS) This register indicates the total transfer byte count of DMA channel n (n = 0 to 15). The value of this register becomes 0 when the transaction ends. The values are loaded from the Next0/1 register set in register mode or from the descriptor read data in link mode.
Page 735 RZ/G3S Group 14. Direct Memory Access Controller 14.4.7 Channel Status Register n/nS (CHSTAT_n/nS) This register indicates the status of DMA channel n (n = 0 to 15). — — — — — — — — — — — — — —...
Page 736 RZ/G3S Group 14. Direct Memory Access Controller Initial Bit Name Value Description Descriptor Load Indicates whether the descriptor is being loaded. The bit maintains 1 if a bus error is received during descriptor load. 0: Operation other than descriptor load 1: (ER = 0) Descriptor load is in progress in link mode.
Page 737 RZ/G3S Group 14. Direct Memory Access Controller Initial Bit Name Value Description Error bit Indicates that a DMA error interrupt has occurred because an error response has been received from the transfer source or destination and a bus error has occurred during the DMA transfer.
Page 738 RZ/G3S Group 14. Direct Memory Access Controller Initial Bit Name Value Description Enable Indicates whether the operation of DMA channel n is enabled or disabled. 0: Operation disabled 1: Operation enabled Set condition(s): ● When SETEN (CHCTRL_n/nS) is set to 1 Clear condition(s): ●...
Page 739 RZ/G3S Group 14. Direct Memory Access Controller 14.4.8 Channel Control Register n/nS (CHCTRL_n/nS) This register controls the DMA transfer operation on DMA channel n (n = 0 to 15). CLRINT SETINT — — — — — — — — — —...
Page 740 RZ/G3S Group 14. Direct Memory Access Controller Initial Bit Name Value Description CLREND Clear End bit Setting this bit to 1 can clear the END bit of the CHSTAT_n/nS register. Also, the DMA transfer end interrupt is cleared. An attempt to read this bit results in 0 being read. 1: Clears the END bit.
Page 741 RZ/G3S Group 14. Direct Memory Access Controller 14.4.9 Channel Configuration Register n/nS (CHCFG_n/nS) This register controls the DMA transfer operation on DMA channel n (n = 0 to 15). RSEL — — — DDS[3:0] Initial Value SDS[3:0] — AM[2:0] — HIEN LOEN REQD...
Page 742 RZ/G3S Group 14. Direct Memory Access Controller Initial Bit Name Value Description DMA Transfer End Interrupt Mask Masks the DMA transfer end interrupt for register mode transfer. If 1 is set in this bit when a DMA transfer end interrupt is output, the DMA transfer end interrupt signal is not asserted.
Page 743 RZ/G3S Group 14. Direct Memory Access Controller Initial Bit Name Value Description — Reserved. Set 0. A read operation results in 0 being read. Level Selects whether to detect a DMA request based on the level or edge of the signal. 0: Detects based on the edge (initial value).
Page 744 RZ/G3S Group 14. Direct Memory Access Controller 14.4.10 Channel Interval Register n/nS (CHITVL_n/nS) This register sets the transfer interval for DMA channel n (n = 0 to 15). For details, see Section 14.7.6, Interval Count Function. — — — — —...
Page 745 RZ/G3S Group 14. Direct Memory Access Controller 14.4.11 Channel Extension Register n/nS (CHEXT_n/nS) This is an extension register for DMA channel n (n = 0 to 15). — — — — — — — — — — — — — —...
Page 746 RZ/G3S Group 14. Direct Memory Access Controller 14.4.12 Next Link Address Register n/nS (NXLA_n/nS) This is a 32-bit register that sets the link address of DMA channel n (n = 0 to 15). For information about the link mode, see Section 14.6.3, Link Mode. NXLA Initial Value NXLA...
Page 747 RZ/G3S Group 14. Direct Memory Access Controller 14.4.14 DMA Control Register (DCTRL_0_7/0_7S, DCTRL_8_15/8_15S) This register sets the transfer type for descriptor access and the arbitration between channels. (DCTRL_0_7/0_7S is common for channels 0 to 7 and DCTRL_8_15/8_15S is common for channels 8 to 15.) LWCA —...
Page 748 RZ/G3S Group 14. Direct Memory Access Controller 14.4.15 DMA Status EN Register (DSTAT_EN_0_7/0_7S) This register indicates the EN bit status of the CHSTAT_n/nS register (n = 0 to 7). Writing to this register does not affect the values of the bits. —...
Page 749 RZ/G3S Group 14. Direct Memory Access Controller 14.4.16 DMA Status EN Register (DSTAT_EN_8_15/8_15S) This register indicates the EN bit status of the CHSTAT_n/nS register (n = 8 to 15). Writing to this register does not affect the values of the bits. —...
Page 750 RZ/G3S Group 14. Direct Memory Access Controller 14.4.17 DMA Status ER Register (DSTAT_ER_0_7/0_7S) This register indicates the ER bit status of the CHSTAT_n/nS register (n = 0 to 7). Writing to this register does not affect the values of the bits. —...
Page 751 RZ/G3S Group 14. Direct Memory Access Controller 14.4.18 DMA Status ER Register (DSTAT_ER_8_15/8_15S) This register indicates the ER bit status of the CHSTAT_n/nS register (n = 8 to 15). Writing to this register does not affect the values of the bits. —...
Page 752 RZ/G3S Group 14. Direct Memory Access Controller 14.4.19 DMA Status END Register (DSTAT_END_0_7/0_7S) This register indicates the END bit status of the CHSTAT_n/nS register (n = 0 to 7). Writing to this register does not affect the values of the bits. —...
Page 753 RZ/G3S Group 14. Direct Memory Access Controller 14.4.20 DMA Status END Register (DSTAT_END_8_15/8_15S) This register indicates the END bit status of the CHSTAT_n/nS register (n = 8 to 15). Writing to this register does not affect the values of the bits. —...
Page 754 RZ/G3S Group 14. Direct Memory Access Controller 14.4.21 DMA Status TC Register (DSTAT_TC_0_7/0_7S) This register indicates the TC bit status of the CHSTAT_n/nS register (n = 0 to 7). Writing to this register does not affect the values of the bits. —...
Page 755 RZ/G3S Group 14. Direct Memory Access Controller 14.4.22 DMA Status TC Register (DSTAT_TC_8_15/8_15S) This register indicates the TC bit status of the CHSTAT_n/nS register (n = 8 to 15). Writing to this register does not affect the values of the bits. —...
Page 756 RZ/G3S Group 14. Direct Memory Access Controller 14.4.23 DMA Status SUS Register (DSTAT_SUS_0_7/0_7S) This register indicates the SUS bit status of the CHSTAT_n/nS register (n = 0 to 7). Writing to this register does not affect the values of the bits. —...
Page 757 RZ/G3S Group 14. Direct Memory Access Controller 14.4.24 DMA Status SUS Register (DSTAT_SUS_8_15/8_15S) This register indicates the SUS bit status of the CHSTAT_n/nS register (n = 8 to 15). Writing to this register does not affect the values of the bits. —...
Page 758 RZ/G3S Group 14. Direct Memory Access Controller 14.4.25 DMA Extension Resource Selectors 0/0S to 7/7S (DMARS0/0S to DMARS7/7S) DMARSn/nS (n = 0 to 7) are 32-bit readable/writable registers that specify the DMA transfer sources from peripheral modules in each channel. DMARS0/0S is for channels 0/0S and 1/1S, DMARS1/1S is for channels 2/2S and 3/3S, and so on.
Page 759 RZ/G3S Group 14. Direct Memory Access Controller DMARS2/2S ● — — — — — — CH5 MID[7:0] CH5 RID[1:0] Initial Value — — — — — — CH4 MID[7:0] CH4 RID[1:0] Initial Value DMARS3/3S ● — — — — — —...
Page 760 RZ/G3S Group 14. Direct Memory Access Controller DMARS5/5S ● — — — — — — CH11 MID[7:0] CH11 RID[1:0] Initial Value — — — — — — CH10 MID[7:0] CH10 RID[1:0] Initial Value DMARS6/6S ● — — — — — —...
Page 761 RZ/G3S Group 14. Direct Memory Access Controller 14.5 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in two modes: auto request, and on-chip peripheral module request.
Page 762 RZ/G3S Group 14. Direct Memory Access Controller 14.5.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated in on-chip peripheral modules that are neither the transfer source nor destination. Transfers can be requested in two modes: auto request, and on-chip peripheral module request.
Page 763 RZ/G3S Group 14. Direct Memory Access Controller Table 14.3 On-Chip Module Requests (1/9) DMA Transfer DMARSn/nS CHCFG_n/nS* DMA Transfer Request Transfer Transfer Request Source Signal Source Destination [7:0] [1:0] [2:0] HIEN LOEN REQD SEL[2:0] GTM ch0 OSTM0TINT Arbitrary Arbitrary 0000_1000 CH0:000 (compare match) CH1:001...
Page 764 RZ/G3S Group 14. Direct Memory Access Controller Table 14.3 On-Chip Module Requests (2/9) DMA Transfer DMARSn/nS CHCFG_n/nS* DMA Transfer Request Transfer Transfer Request Source Signal Source Destination [7:0] [1:0] [2:0] HIEN LOEN REQD SEL[2:0] MTU3 ch4 TGIA4 Arbitrary Arbitrary 0001_1100 CH0:000 (input capture/compare CH1:001...
Page 765 RZ/G3S Group 14. Direct Memory Access Controller Table 14.3 On-Chip Module Requests (3/9) DMA Transfer DMARSn/nS CHCFG_n/nS* DMA Transfer Request Transfer Transfer Request Source Signal Source Destination [7:0] [1:0] [2:0] HIEN LOEN REQD SEL[2:0] MTU3 ch8 TGIA8 Arbitrary Arbitrary 0010_1101 CH0:000 (input capture/compare CH1:001...
Page 766 RZ/G3S Group 14. Direct Memory Access Controller Table 14.3 On-Chip Module Requests (4/9) DMA Transfer DMARSn/nS CHCFG_n/nS* DMA Transfer Request Transfer Transfer Request Source Signal Source Destination [7:0] [1:0] [2:0] HIEN LOEN REQD SEL[2:0] PWM(GPT) ch1 OVF1 Arbitrary Arbitrary 0100_0110 CH0:000 (overflow) CH1:001...
Page 767 RZ/G3S Group 14. Direct Memory Access Controller Table 14.3 On-Chip Module Requests (5/9) DMA Transfer DMARSn/nS CHCFG_n/nS* DMA Transfer Request Transfer Transfer Request Source Signal Source Destination [7:0] [1:0] [2:0] HIEN LOEN REQD SEL[2:0] PWM(GPT) ch4 CCMPA4 Arbitrary Arbitrary 0110_0101 CH0:000 (input capture/compare CH1:001...
Page 768 RZ/G3S Group 14. Direct Memory Access Controller Table 14.3 On-Chip Module Requests (6/9) DMA Transfer DMARSn/nS CHCFG_n/nS* DMA Transfer Request Transfer Transfer Request Source Signal Source Destination [7:0] [1:0] [2:0] HIEN LOEN REQD SEL[2:0] PWM(GPT) ch6 CCMPA6 Arbitrary Arbitrary 0111_1111 CH0:000 (input capture/compare CH1:001...
Page 769 RZ/G3S Group 14. Direct Memory Access Controller Table 14.3 On-Chip Module Requests (7/9) DMA Transfer DMARSn/nS CHCFG_n/nS* DMA Transfer Request Transfer Transfer Request Source Signal Source Destination [7:0] [1:0] [2:0] HIEN LOEN REQD SEL[2:0] SSIF ch0 INT_ssif_dma_rx_0 SSIF Arbitrary 1001_1001 CH0:000 (receive data full) RDR_0...
Page 770 RZ/G3S Group 14. Direct Memory Access Controller Table 14.3 On-Chip Module Requests (8/9) DMA Transfer DMARSn/nS CHCFG_n/nS* DMA Transfer Request Transfer Transfer Request Source Signal Source Destination [7:0] [1:0] [2:0] HIEN LOEN REQD SEL[2:0] INTHRESP (Response Arbitrary 1010_1011 CH0:000 buffer full (high criteria)) HRSPQP CH1:001 IITHCMD (Command...
Page 771 RZ/G3S Group 14. Direct Memory Access Controller Table 14.3 On-Chip Module Requests (9/9) DMA Transfer DMARSn/nS CHCFG_n/nS* DMA Transfer Request Transfer Transfer Request Source Signal Source Destination [7:0] [1:0] [2:0] HIEN LOEN REQD SEL[2:0] RSPI ch0 SPRI0 SPDR0 Arbitrary 1011_0110 CH0:000 (receive buffer full) CH1:001...
Page 772 RZ/G3S Group 14. Direct Memory Access Controller Note 1. CHCFG_n/nS setting value 0: Single transfer 1: Block transfer 001: ACK level output 010: ACK bus cycle output 100: No ACK 0: REQ edge detection 1: REQ level detection REQD 0: ACK output at read 1: ACK output at write Note 2.
Page 773 RZ/G3S Group 14. Direct Memory Access Controller 14.6 DMA Mode 14.6.1 Mode Setting The DMS field of the CHCFG_n/nS register can be used to toggle between register mode and link mode. Table 14.4 DMA Mode Setting (CHCFG_n/nS) Mode Description Register mode A DMA transfer is executed using the values set in the Next Register Set.
Page 774 RZ/G3S Group 14. Direct Memory Access Controller 14.6.2 Register Mode In register mode, a DMA transfer is executed using the values set in the internal registers. Two sets of the source address, destination address, and transfer byte count (Next0 Register Set and Next1 Register Set) can be set.
Page 775 RZ/G3S Group 14. Direct Memory Access Controller (1) Operation Flow Setup by software Set channel_ Set channel enable configurations SETEN = 1 Processing by hardware Bus transaction Register set selection RSEL Load Next0 Register Set to Load Next1 Register Set to Current Register Set Current Register Set N0SA →...
Page 776 RZ/G3S Group 14. Direct Memory Access Controller DMA transaction (processing transaction) A DMA transfer is executed according to the set values. For details of the transfer, see Section 14.7, DMA Transfer. DMA transfer end interrupt mask (DMAINT mask) The DMA transfer end interrupt is masked according to the value set in the DEM bit of CHCFG_n/nS. When 1 is set in DEM, the DMA transfer end interrupt is not output.
Page 777 RZ/G3S Group 14. Direct Memory Access Controller (c) Automatic register set execution setting After DMA transfers, the DMA transaction of the selected register set is automatically executed. Table 14.7 Automatic Register Set Execution Setting (CHCFG_n/nS) Operation Remark When the DMA transaction of the register set selected by RSEL is Set this value to execute a DMA completed, the EN bit is cleared and the DMA operation ends.
Page 778 RZ/G3S Group 14. Direct Memory Access Controller (3) Setting Examples (a) When only the Next0 register set is used Table 14.9 Register Mode Setting Example 1 RSEL (CHCFG_n/nS) (CHCFG_n/nS) (CHCFG_n/nS) (CHCFG_n/nS) (CHCFG_n/nS) (Register mode) (Next0) (not masked) (not switched) (not continuously executed) DMA Channel n 3.
Page 779 RZ/G3S Group 14. Direct Memory Access Controller (b) When two register sets are used continuously Table 14.10 Automatic Register Set Execution Setting RSEL (CHCFG_n/nS) (CHCFG_n/nS) (CHCFG_n/nS) (CHCFG_n/nS) (CHCFG_n/nS) (Register mode) (Next0) (masked) (switched) (continuously executed) Next0 Register Set 6. DMAEND Source Address Current Register Set Destination Address...
Page 780 RZ/G3S Group 14. Direct Memory Access Controller 14.6.3 Link Mode In link mode, a descriptor stored in external memory is loaded as set values and a DMA transaction is executed using the loaded values. The DMAC contains a Next Link address and a Current Link address for each channel, and these addresses are used to set the descriptor address to be executed next and to indicate the descriptor address of the currently executed DMA transaction, respectively.
Page 781 RZ/G3S Group 14. Direct Memory Access Controller (1) Operation Flow Setup by software Processing by hardware Set channel enable Bus transaction Set link address SETEN = 1 Reflect descriptor data to registers Update link Update registers address Update current link address Descriptor data NXLA CRLA...
Page 782 RZ/G3S Group 14. Direct Memory Access Controller Link address update When 1 is set in EN (1 is set in SETEN), the Link address set in NXLA_n/nS is loaded to CRLA_n/nS. Descriptor load and header analysis The DMAC begins to load the descriptor and then analyzes the content of the header. When LV is 0, the DMAC discards the loaded descriptor and sets 1 in DER to end the operation (EN = 0).
Page 783 RZ/G3S Group 14. Direct Memory Access Controller (2) Register Setting (a) Link mode setting To use the link mode, set 1 in the DMS bit of the CHCFG_n/nS register. Table 14.11 Link Mode Setting (CHCFG_n/nS) Description Operates in link mode. This bit cannot be changed using a descriptor.
Page 784 RZ/G3S Group 14. Direct Memory Access Controller (3) Descriptor Setting In a link address, prepare a descriptor with data arranged in the order shown below. The DMAC reads the descriptor in burst mode. (a) Descriptor data arrangement Table 14.13 Descriptor Data Arrangement Address Data Remarks...
Page 785 RZ/G3S Group 14. Direct Memory Access Controller Table 14.14 Header Area Bit Position Bit Name Meaning 31 to 4 — — Descriptor Interrupt Mask Sets whether to mask the DMA transfer end interrupt if 0 is set in LV when the header is loaded. 0: Issues a DMA transfer end interrupt.
Page 786 RZ/G3S Group 14. Direct Memory Access Controller (e) Descriptor area and DMA transfer area The following figure outlines the descriptor area and DMA transfer area that are accessed by the DMAC. External memory or on-chip memory space [31:0] descriptor 1 header DMAC (1) Descriptor read...
Page 787 RZ/G3S Group 14. Direct Memory Access Controller Descriptor read When 0 is set in the LE bit of the header in the last read descriptor (<1>), the next descriptor is read from the address (descriptor2) indicated by Next Link Address in the descriptor. DMA transfer When 1 is set in the LV bit of the header in the descriptor, a DMA transfer is executed according to the descriptor data.
Page 788 RZ/G3S Group 14. Direct Memory Access Controller (4) Descriptor Configuration Examples In link mode, a descriptor can be configured as shown below. List configuration Loop configuration External memory or on-chip memory space External memory or on-chip memory space header (LE = 0) header (LE = 0) H’00 H’00...
Page 789 RZ/G3S Group 14. Direct Memory Access Controller 14.7 DMA Transfer The basic operation of DMA transfer is described here. 14.7.1 Transfer Mode Two transfer modes are supported: single transfer mode and block transfer mode. To select a transfer mode, set the TM bit of CHCFG_n/nS for each channel. Table 14.15 Basic Transfer Setting Transfer Mode...
Page 790 RZ/G3S Group 14. Direct Memory Access Controller 14.7.2 Priority Control for DMA Channels Within channels 0 to 7 and 8 to 15, two priority control modes are supported: fixed priority mode and round robin mode. Only round robin mode is supported for priority control between the group of channels 0 to 7 and the group of channels 8 to 15.
Page 791 RZ/G3S Group 14. Direct Memory Access Controller Channels 4 to 7: Not used DMAREQ[0] Channel 0 DMAACK[0] DMAREQ[1] Channel 1 DMAACK[1] DMAREQ[2] Channel 2 DMAACK[2] DMAREQ[3] Channel 3 DMAACK[3] Request execution order Read execution channel Write execution channel Figure 14.13 Fixed Priority Mode (Number of Channels = 4, REQD = 1) R01UH1014EJ0110 Rev.1.10...
Page 792 RZ/G3S Group 14. Direct Memory Access Controller (2) Round Robin Mode In round robin mode, each time a transfer request is received from a channel in the group of channels 0 to 7 and the group of channels 8 to 15, the order of priority is changed in such a way that the channel that executed a transfer last has the lowest priority.
Page 793 RZ/G3S Group 14. Direct Memory Access Controller 14.7.3 DMA Transfer Request Edge detection or level detection can be selected using the LVL bit of the CHCFG_n/nS register. The HIEN and LOEN bits of the CHCFG_n/nS register are used to select either the rising edge or falling edge in the case of edge detection or either the high level or low level in the case of level detection.
Page 794 RZ/G3S Group 14. Direct Memory Access Controller 14.7.5 DMA Error Interrupt If an error response is received for a DMA transfer or descriptor access, the DMAC regards it as an error and stops the transfer. Upon receiving an error response, the EN bit of the CHSTAT_n/nS register of transferring channel n is cleared to 0 and 1 is set in the ER bit (n = 0 to 15).
Page 795 RZ/G3S Group 14. Direct Memory Access Controller 14.7.7 Difference in Operation Due to the Transfer Size (1) When the Source Transfer Size Is Smaller When the read of data equivalent to the destination data size is completed, the data is written to the destination. The following figure shows a timing chart where the source transfer size is 8 bits and the destination transfer size is 32 bits (in the case of rising edge detection).
Page 796 RZ/G3S Group 14. Direct Memory Access Controller (3) When the Source Transfer Size Is the Same as the Destination Transfer Size Every time a DMA transfer request is detected, a source read and a destination write occur. The following figure shows a timing chart where the source transfer size and the destination transfer size are both 8 bits (in the case of rising edge detection, with 1 set in REQD of the CHCFG_n/nS register).
Page 797 RZ/G3S Group 14. Direct Memory Access Controller 14.7.8 Transfer Status The channel status register indicates the status of DMA transfer execution on a channel. (1) Suspend A DMA transfer can be suspended by using the SETSUS bit of CHCTRL_n/nS. In this case, if an ongoing bus cycle exists, the DMAC waits for that cycle to end before suspending the transfer.
Page 798 RZ/G3S Group 14. Direct Memory Access Controller (a) Transfer Stop (Buffer Sweep Disabled - SBE = 0) If 1 is set in CLREN during a DMA transfer, the DMA transfer is stopped. The stop timing depends on the value set in REQD.
Page 799 RZ/G3S Group 14. Direct Memory Access Controller (b) Transfer Stop (Buffer Sweep Enabled - SBE = 1) If 1 is set in CLREN during a DMA transfer, the DMA transfer is stopped. When 0 is set in REQD, the DMA transfer is stopped after the DMAC sweeps (writes) the already read data.
Page 800 RZ/G3S Group 14. Direct Memory Access Controller When 0 is set in SBE, the transfer is stopped according to the value of REQD. When 1 is set in SBE, the sweep mode is enabled. When 1 is set in SBE, set 0 in REQD. Read CHSTAT_n/nS to check that 0 is set in the TACT bit.
Page 801 RZ/G3S Group 14. Direct Memory Access Controller 14.8 DMA Setting Examples Setting examples applicable when DMA transfer is executed using the direct memory access controller are shown in the following. The transfer conditions for these setting examples are as follows. Table 14.18 Transfer Condition List for DMA Transfer Setting Examples DMA Mode...
Page 802 RZ/G3S Group 14. Direct Memory Access Controller Start (setting example 1) DCTRL ← H’0000_0000  Fixed priority N0SA_3 ← H’1111_0000  Source: H’1111_0000 N0DA_3 ← H’2222_0000  Destination: H’2222_0000 N0TB_3 ← H’0000_0040  Transfer size: 64 bytes CHCFG_3 ← H’0002_2123 ...
Page 803 RZ/G3S Group 14. Direct Memory Access Controller 14.8.2 Setting Example 2 (Register Mode/Software Request) The following table shows a setting example applicable when DMA transfer is executed using the settings shown below. Table 14.20 DMA Transfer Setting Example 2 Item Description Channel used Priority control...
Page 804 RZ/G3S Group 14. Direct Memory Access Controller Start (setting example 2) DCTRL ← H’0000_0001  Round-robin N1SA_2 ← H’0FFF_E000  Source: H’0FFF_E000 N1DA_2 ← H’3333_0000  Destination: H’3333_0000 N1TB_2 ← H’0000_0080  Transfer size: 128 bytes CHCFG_2 ← H’1045_0402  Interval: None CHITVL_2 ←...
Page 805 RZ/G3S Group 14. Direct Memory Access Controller 14.8.3 Setting Example 3 (Register Mode/Continuous Execution) The following table shows a setting example applicable when DMA transfer is executed using the settings shown below. Table 14.21 DMA Transfer Setting Example 3 Item Description Channel used Priority control...
Page 806 RZ/G3S Group 14. Direct Memory Access Controller Start (setting example 3) DCTRL ← H’0000_0001  Round-robin N0SA_1 ← H’1111_0000  Source: H’1111_0000 N0DA_1 ← H’3333_0000  Destination: H’3333_0000 N0TB_1 ← H’0000_0200  Transfer size: 512 bytes N1SA_1 ← H’2222_0000  Source: H'2222_0000 N1DA_1 ←...
Page 807 RZ/G3S Group 14. Direct Memory Access Controller 14.8.4 Setting Example 4 (Link Mode) The following table shows a setting example applicable when DMA transfer is executed using the settings shown below. Table 14.22 DMA Transfer Setting Example 4 Item Description Channel used Priority control Round robin...
Page 808 RZ/G3S Group 14. Direct Memory Access Controller Table 14.24 DMA Transfer Setting Example 4 (Descriptor 2) Item Description Descriptor start address H’0000_2000 Next descriptor start address H’0000_5000 Transfer mode Block transfer Next0 Source Destination Start address H’4444_0000 H’5555_0000 Address direction Increment Increment Data size...
Page 809 RZ/G3S Group 14. Direct Memory Access Controller Table 14.26 Descriptor Setting Descriptor 1 Descriptor 2 Descriptor 3 header H’0000_0001 H’0000_0001 H’0000_0003 SA (Source Address) H’1111_0000 H’4444_0000 H’7777_0000 DA (Destination Address) H’3333_0000 H’5555_0000 H’AAAA_0000 TB (Transaction Byte) H’0000_0800 H’0000_0400 H’0000_1000 CFG (Configuration) H’8142_2008 H’8145_3008 H’8046_6008...
Page 810 RZ/G3S Group 14. Direct Memory Access Controller 14.8.5 Next Register Set Continuous Execution Setting The following figure shows the flowchart for executing DMA transfers continuously by using two Next register sets in register mode. While a DMA transaction is being executed using one Next register set, the other Next register set is set in order to continue to execute DMA transfers.
Page 811 RZ/G3S Group 14. Direct Memory Access Controller Start Set DCTRL Set CHITVL Set CHEXT $CR = 0 Set CHCFG_n/nS (other settings are optional) REN = 1, RSW = 1, 　　 RSEL = $CR, DEM = 0 Set register 0 (N0SA, N0DA, N0TB) $CR (current register): Set register 1 (N1SA, N1DA, N1TB) This variable is for RSEL control.
Page 812 RZ/G3S Group 14. Direct Memory Access Controller Supplementary information ● First, save the data of the register sets to be used for DMA transfers (0 (N0SA, N0DA, and N0TB) and 1 (N1SA, N1DA, and N1TB)) to a general-purpose register of the CPU (the values of this register is referred to as $CR for the sake of convenience).
Page 813 RZ/G3S Group 15. System Counter (SYC) 15. System Counter (SYC) SYC generates the count value used by the generic timer built into Cortex-A55. It uses the Timestamp generator, which is one of the components of Arm CoreSight SoC-400, to generate a 64-bit count value.
Page 814 RZ/G3S Group 15. System Counter (SYC) 15.1.2 Block Diagram of SYC The SYC connection diagram is shown in Figure 15.1 and the SYC block diagram is shown in Figure 15.2. SYC_CNT_CLK Count output Cortex-A55 Reset Halt on Debug control signal CoreSight System Bus Figure 15.1...
Page 815 RZ/G3S Group 15. System Counter (SYC) 15.2 Address Space Table 15.1 shows the SYC address space. SYC has an address space of 8 KB. The SYC address space is offset from the base address. The base address of SYC is as follows. SYC base address: H’0_1100_0000 (Overall Address Space) SYC base address: H’4100_0000 (Cortex-M33/Cortex-M33_FPU Address Space Secure) SYC base address: H’5100_0000 (Cortex-M33/Cortex-M33_FPU Address Space Non-Secure)
Page 816 RZ/G3S Group 15. System Counter (SYC) 15.4 Operation 15.4.1 System Bus Access Control Access control from one system bus interface of SYC to two APB interfaces of Timestamp Generator is performed. Controls so that the PSELCTRL area can be accessed when accessing the first half 4 KB of the 8 KB address area of SYC, and the PSELREAD area can be accessed when accessing the latter 4 KB.
Page 817 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.1 Overview This LSI has an on-chip multi-function timer pulse unit 3 (MTU3a), consisting of eight 16-bit timer channels and one 32- bit timer channel. Table 16.1 shows the specifications of the MTU and Table 16.2 lists the functions of the MTU.
Page 818 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.1 MTU Specifications (2/2) Item Description Trigger generation A/D converter start triggers can be generated A/D converter start request delaying function enables A/D converter to be started with any desired timing and to be synchronized with PWM output Low power consumption function The MTU3a can be placed in the module-stop state.
Page 819 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.2 MTU Functions (2/2) MTU1 & MTU2 Item MTU0 MTU1 MTU2 (LWA = 1) MTU3 MTU4 MTU5 MTU6 MTU7 MTU8 A/D converter start trigger TGRA TGRA TGRA TGRALW TGRA TGRA —...
Page 820 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Interrupt request signals MTU3: TGIA3 TGIB3 TGIC3 I/O pins TGID3 MTU3: MTIOC3A TCIV3 MTIOC3B MTIOC3C MTU4: TGIA4 MTIOC3D TGIB4 TGIC4 MTU4: MTIOC4A TGID4 MTIOC4B TCIV4 MTIOC4C MTIOC4D Clock input Internal clock: P0φ P0φ/2 P0φ/4 P0φ/8...
Page 821 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Interrupt request signals MTU6: TGIA6 TGIB6 TGIC6 I/O pins TGID6 MTU6: MTIOC6A TCIV6 MTIOC6B MTIOC6C MTU7: TGIA7 MTIOC6D TGIB7 TGIC7 MTU7: MTIOC7A TGID7 MTIOC7B TCIV7 MTIOC7C MTIOC7D Interrupt request signals MTU5: TGIU5 Input pins TGIV5 TGIW5...
Page 822 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.3 shows the configuration of pins for the MTU. Table 16.3 Pin Configuration of the MTU Channel Pin Name Function MTCLKA Input External clock A input pin (MTU1/MTU2 phase counting mode A phase input) MTCLKB Input External clock B input pin (MTU1/MTU2 phase counting mode B phase input)
Page 823 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2 Register Descriptions Table 16.4 shows the register configuration. The MTU address space is offset from the base address. The base address of MTU is as follows. MTU base address: H’0_1000_0000 (Overall Address Space) MTU base address: H’4000_0000 (Cortex-M33/Cortex-M33_FPU Address Space Secure) MTU base address: H’5000_0000 (Cortex-M33/Cortex-M33_FPU Address Space Non-Secure) Remark...
Page 824 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.4 Register configuration (2/5) Channel Register Name Abbreviation Address Access size MTU2 Timer control register H’1400 Timer mode register 1 TMDR1 H’1401 Timer I/O control register TIOR H’1402 Timer interrupt enable register TIER H’1404 Timer status register...
Page 825 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.4 Register configuration (3/5) Channel Register Name Abbreviation Address Access size MTU4 Noise filter control register 4 NFCR4 H’1294 MTU5 Timer counter U TCNTU H’1C80 Timer general register U TGRU H’1C82 Timer control register U TCRU...
Page 826 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.4 Register configuration (4/5) Channel Register Name Abbreviation Address Access size MTU7 Timer general register D TGRD H’1A2A Timer control register 2 TCR2 H’1A4D Timer general register E TGRE H’1A74 Timer general register F TGRF H’1A76...
Page 827 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.4 Register configuration (5/5) Channel Register Name Abbreviation Address Access size Timer output master enable register B TOERB H’1A0A Timer output control register 1B TOCR1B H’1A0E Timer output control register 2B TOCR2B H’1A0F Timer cycle data register B...
Page 828 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.1 Timer Control Register (TCR) (1) MTU0.TCR, MTU1.TCR, MTU2.TCR, MTU3.TCR, MTU4.TCR, MTU6.TCR, MTU7.TCR, MTU8.TCR Address(es): MTU0.TCR H’0_1000_1300, MTU1.TCR H’0_1000_1380, MTU2.TCR H’0_1000_1400, MTU3.TCR H’0_1000_1200, MTU4.TCR H’0_1000_1201, MTU6.TCR H’0_1000_1A00, MTU7.TCR H’0_1000_1A01, MTU8.TCR H’0_1000_1600 CCLR[2:0] CKEG[1:0] TPSC[2:0]...
Page 829 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.5 CCLR[2:0] (MTU0, MTU3, MTU4, MTU6, MTU7, and MTU8) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description MTU0 TCNT clearing disabled MTU3 TCNT cleared by TGRA compare match/input capture MTU4 TCNT cleared by TGRB compare match/input capture MTU6...
Page 830 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.2 Timer Control Register 2 (TCR2) (1) MTU0.TCR2, MTU3.TCR2, MTU4.TCR2, MTU6.TCR2, MTU7.TCR2, MTU8.TCR2 Address(es): MTU0.TCR2 H’0_1000_1328, MTU3.TCR2 H’0_1000_124C, MTU4.TCR2 H’0_1000_124D, MTU6.TCR2 H’0_1000_1A4C, MTU7.TCR2 H’0_1000_1A4D, MTU8.TCR2 H’0_1000_1606 — — — — — TPSC2[2:0] Initial Value (2) MTU1.TCR2, MTU2.TCR2...
Page 831 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (3) MTU5.TCR2U, MTU5.TCR2V, MTU5.TCR2W Address(es): MTU5.TCR2U H’0_1000_1C85, MTU5.TCR2V H’0_1000_1C95, MTU5.TCR2W H’0_1000_1CA5 — — — CKEG[1:0] TPSC2[2:0] Initial Value Initial Bit Name Value Description b2 to b0 TPSC2[2:0] All 0 Time Prescaler Select See Table 16.11.
Page 832 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.7 TPSC[2:0], TPSC2[2:0] (MTU0) TCR2[2:0] TCR[2:0] Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 Channel TPSC22 TPSC21 TPSC20 TPSC2 TPSC1 TPSC0 Description MTU0 Internal clock: counts on P0φ/1 Internal clock: counts on P0φ/4 Internal clock: counts on P0φ/16 Internal clock: counts on P0φ/64...
Page 833 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.9 TPSC[2:0], TPSC2[2:0] (MTU2) TCR2[2:0] TCR[2:0] Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 Channel TPSC22 TPSC21 TPSC20 TPSC2 TPSC1 TPSC0 Description MTU2 Internal clock: counts on P0φ/1 Internal clock: counts on P0φ/4 Internal clock: counts on P0φ/16 Internal clock: counts on P0φ/64...
Page 834 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.11 TPSC[1:0], TPSC2[2:0] (MTU5) TCR2[2:0] TCR[1:0] Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 Channel TPSC22 TPSC21 TPSC20 TPSC1 TPSC0 Description MTU5 Internal clock: counts on P0φ/1 Internal clock: counts on P0φ/4 Internal clock: counts on P0φ/16 Internal clock: counts on P0φ/64 Internal clock: counts on P0φ/2...
Page 835 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.3 Timer Mode Register 1 (TMDR1) (1) MTU0.TMDR1 Address(es): MTU0.TMDR1 H’0_1000_1301 — MD[3:0] Initial Value (2) MTU1.TMDR1, MTU2.TMDR1 Address(es): MTU1.TMDR1 H’0_1000_1381, MTU2.TMDR1 H’0_1000_1401 — — — — MD[3:0] Initial Value (3) MTU3.TMDR1, MTU4.TMDR1, MTU6.TMDR1, MTU7.TMDR1, MTU8.TMDR1 Address(es): MTU3.TMDR1 H’0_1000_1202, MTU4.TMDR1 H’0_1000_1203, MTU6.TMDR1 H’0_1000_1A02, MTU7.TMDR1 H’0_1000_1A03, MTU8.TMDR1 H’0_1000_1601...
Page 836 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) The TMDR1 register specifies the operating mode of each channel. The MTU has a total of eight TMDR1 registers, one each for MTU0 to MTU4, MTU 6, MTU7, and MTU8. TMDR1 register values should be specified only while TCNT operation is stopped.
Page 837 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) BFB Bit (Buffer Operation B) This bit specifies whether to operate TGRB in the normal way or to use TGRB and TGRD together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare does not take place in modes other than complementary PWM mode, but compare match with TGRD occurs in complementary PWM mode.
Page 838 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.4 Timer Mode Registers 2 (TMDR2A and TMDR2B) Address(es): MTU.TMDR2A H’0_1000_1270, MTU.TMDR2B H’0_1000_1A70 — — — — — — — Initial Value Initial Bit Name Value Description Double Buffer Select 0: Double buffer function is disabled 1: Double buffer function is enabled b7 to b1 —...
Page 839 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.5 Timer Mode Register 3 (TMDR3) Address(es): MTU1.TMDR3 H’0_1000_1391 PHCKS — — — — — — Initial Value Initial Bit Name Value Description MTU1/MTU2 Combination Longword Access Control 0: 16-bit access is enabled. 1: 32-bit access is enabled.
Page 840 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.13 Setting and Combination of the TMDR3 Register TMDR3.LWA = 0 TMDR3.LWA = 1 Register Symbol Access mode Symbol Access mode Counter in MTU1* MTU1.TCNT Word MTU1.TCNT_1_LW Longword Counter in MTU2 MTU2.TCNT Word General register A in MTU1...
Page 841 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.6 Timer I/O Control Register (TIOR) (1) MTU0.TIORH, MTU1.TIOR, MTU2.TIOR, MTU3.TIORH, MTU4.TIORH, MTU6.TIORH, MTU7.TIORH, MTU8.TIORH Address(es): MTU0.TIORH H’0_1000_1302, MTU1.TIOR H’0_1000_1382, MTU2.TIOR H’0_1000_1402, MTU3.TIORH H’0_1000_1204, MTU4.TIORH H’0_1000_1206, MTU6.TIORH H’0_1000_1A04, MTU7.TIORH H’0_1000_1A06, MTU8.TIORH H’0_1000_1602 IOB[3:0] IOA[3:0] Initial Value...
Page 842 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU0.TIORL, MTU3.TIORL, MTU4.TIORL, MTU6.TIORL, MTU7.TIORL, MTU8.TIORL Address(es): MTU0.TIORL H’0_1000_1303, MTU3.TIORL H’0_1000_1205, MTU4.TIORL H’0_1000_1207, MTU6.TIORL H’0_1000_1A05,MTU7.TIORL H’0_1000_1A07, MTU8.TIORL H’0_1000_1603 IOD[3:0] IOC[3:0] Initial Value Initial Bit Name Value Description b3 to b0 IOC[3:0] All 0 I/O Control C*...
Page 843 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) The TIOR register controls the TGR register. The MTU has a total of 17 TIOR registers, two each for MTU0, MTU3, MTU4, MTU6, MTU7, and MTU8, one each for MTU1 and MTU2, and three (MTU5.TIORU/TIORV/TIORW) for MTU5.
Page 844 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.15 TIORL (MTU0) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD3 IOD2 IOD1 IOD0 MTU0.TGRD Function MTIOC0D Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 845 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.16 TIOR (MTU1) Bit 7 Bit 6 Bit 5 Bit 4 Description MTU1.TGRB/TGRBLW Function IOB3 IOB2 IOB1 IOB0 MTIOC1B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 846 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.18 TIORH (MTU3) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB3 IOB2 IOB1 IOB0 MTU3.TGRB Function MTIOC3B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 847 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.20 TIORH (MTU4) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB3 IOB2 IOB1 IOB0 MTU4.TGRB Function MTIOC4B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 848 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.22 TIORH (MTU6) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB3 IOB2 IOB1 IOB0 MTU6.TGRB Function MTIOC6B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 849 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.24 TIORH (MTU7) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB3 IOB2 IOB1 IOB0 MTU7.TGRB Function MTIOC7B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 850 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.26 TIORH (MTU8) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB3 IOB2 IOB1 IOB0 MTU8.TGRB Function MTIOC8B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 851 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.28 TIORH (MTU0) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA3 IOA2 IOA1 IOA0 MTU0.TGRA Function MTIOC0A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 852 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.29 TIORL (MTU0) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC3 IOC2 IOC1 IOC0 MTU0.TGRC Function MTIOC0C Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 853 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.30 TIOR (MTU1) Bit 3 Bit 2 Bit 1 Bit 0 Description MTU1.TGRA/TGRALW Function IOA3 IOA2 IOA1 IOA0 MTIOC1A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 854 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.32 TIORH (MTU3) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA3 IOA2 IOA1 IOA0 MTU3.TGRA Function MTIOC3A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 855 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.34 TIORH (MTU4) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA3 IOA2 IOA1 IOA0 MTU4.TGRA Function MTIOC4A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 856 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.36 TIORH (MTU6) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA3 IOA2 IOA1 IOA0 MTU6.TGRA Function MTIOC6A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 857 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.38 TIORH (MTU7) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA3 IOA2 IOA1 IOA0 MTU7.TGRA Function MTIOC7A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 858 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.40 TIORH (MTU8) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA3 IOA2 IOA1 IOA0 MTU8.TGRA Function MTIOC8A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 859 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.42 TIORU, TIORV, and TIORW (MTU5) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description MTU5.TGRU, MTU5.TGRV, IOC4 IOC3 IOC2 IOC1 IOC0 MTU5.TGRW Function MTIC5U, MTIC5V, MTIC5W Pin Function Output compare register No function Setting prohibited...
Page 860 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.7 Timer Compare Match Clear Register (TCNTCMPCLR) Address(es): MTU5.TCNTCMPCLR H’0_1000_1CB6 CMPCL CMPCL CMPCL — — — — — Initial Value Initial Bit Name Value Description CMPCLR5W TCNT Compare Clear 5W 0: Disables MTU5.TCNTW to be cleared to H’0000 at MTU5.TCNTW and MTU5.TGRW compare match or input capture 1: Enables MTU5.TCNTW to be cleared to H’0000 at MTU5.TCNTW and MTU5.TGRW compare match or input capture...
Page 861 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.8 Timer Interrupt Enable Register (TIER) (1) MTU1.TIER, MTU2.TIER Address(es): MTU1.TIER H’0_1000_1384, MTU2.TIER H’0_1000_1404 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial Value (2) MTU0.TIER, MTU3.TIER, MTU6.TIER Address(es): MTU0.TIER H’0_1000_1304, MTU3.TIER H’0_1000_1208, MTU6.TIER H’0_1000_1A08 TTGE —...
Page 862 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Initial Bit Name Value Description TGIEA TGR Interrupt Enable A 0: Interrupt requests (TGIA) disabled 1: Interrupt requests (TGIA) enabled TGIEB TGR Interrupt Enable B 0: Interrupt requests (TGIB) disabled 1: Interrupt requests (TGIB) enabled TGIEC TGR Interrupt Enable C 0: Interrupt requests (TGIC) disabled...
Page 863 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) TTGE2 Bit (A/D Converter Start Request Enable 2) This bit enables or disables generation of A/D converter start requests by MTUn.TCNT underflow (trough) in complementary PWM mode (n = 4, 7). In MTU0 to MTU3, MTU6, and MTU8, this bit is reserved.
Page 864 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (6) MTU5.TIER Address(es): MTU5.TIER H’0_1000_1CB2 — — — — — TGIE5U TGIE5V TGIE5W Initial Value Initial Bit Name Value Description TGIE5W TGR Interrupt Enable 5W 0: Interrupt requests TGIW5 disabled 1: Interrupt requests TGIW5 enabled TGIE5V TGR Interrupt Enable 5V 0: Interrupt requests TGIV5 disabled...
Page 865 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.9 Timer Status Register (TSR) (1) MTU1.TSR, MTU2.TSR Address(es): MTU1.TSR H’0_1000_1385, MTU2.TSR H’0_1000_1405 TCFD — — — — — — — Initial Value (2) MTU3.TSR, MTU4.TSR, MTU6.TSR, MTU7.TSR Address(es): MTU3.TSR H’0_1000_122C, MTU4.TSR H’0_1000_122D, MTU6.TSR H’0_1000_1A2C, MTU7.TSR H’0_1000_1A2D TCFD —...
Page 866 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.10 Timer Buffer Operation Transfer Mode Register (TBTM) (1) MTU0.TBTM Address(es): MTU0.TBTM H’0_1000_1326 — — — — — TTSE TTSB TTSA Initial Value (2) MTU3.TBTM, MTU4.TBTM, MTU6.TBTM, MTU7.TBTM Address(es): MTU3.TBTM H’0_1000_1238, MTU4.TBTM H’0_1000_1239, MTU6.TBTM H’0_1000_1A38, MTU7.TBTM H’0_1000_1A39 —...
Page 867 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) TTSB Bit (Timing Select B) This bit specifies the timing for transferring data from TGRD to TGRB in each channel when they are used together for buffer operation. When a channel is not set to PWM mode, do not set the TTSB bit in the channel to 1. TTSE Bit (Timing Select E) This bit specifies the timing for transferring data from MTU0.TGRF to MTU0.TGRE when they are used together for buffer operation.
Page 868 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.11 Timer Input Capture Control Register (TICCR) Address(es): MTU1.TICCR H’0_1000_1390 — — — — I2BE I2AE I1BE I1AE Initial Value Initial Bit Name Value Description I1AE Input Capture Enable 0: Does not include the MTIOC1A pin in the MTU2.TGRA input capture conditions 1: Includes the MTIOC1A pin in the MTU2.TGRA input capture conditions I1BE Input Capture Enable...
Page 869 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.12 Timer Synchronous Clear Register (TSYCR) Address(es): MTU6.TSYCR H’0_1000_1A50 CE0A CE0B CE0C CE0D CE1A CE1B CE2A CE2B Initial Value Initial Bit Name Value Description CE2B Clear Enable 2B 0: Disables counter clearing by the MTU2.TGIB2 interrupt generation timing. 1: Enables counter clearing by the MTU2.TGIB2 interrupt generation timing.
Page 870 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.13 Timer Counter (TCNT) (1) MTU0.TCNT to MTU7.TCNT Address(es): MTU0.TCNT H’0_1000_1306, MTU1.TCNT H’0_1000_1386, MTU2.TCNT H’0_1000_1406, MTU3.TCNT H’0_1000_1210, MTU4.TCNT H’0_1000_1212, MTU5.TCNTU H’0_1000_1C80, MTU5.TCNTV H’0_1000_1C90, MTU5.TCNTW H’0_1000_1CA0, MTU6.TCNT H’0_1000_1A10, MTU7.TCNT H’0_1000_1A12 Initial Value Note: TCNT must not be accessed in eight bits;...
Page 871 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.14 Timer Longword Counter (TCNTLW) Address(es): MTU1.TCNTLW H’0_1000_13A0 Initial Value Initial Value Note: TCNTLW must not be accessed in 8 or 16 bits; it should be accessed in 32 bits. The TCNTLW counter is a 32-bit readable/writable counter. Only one counter of this type is provided, and is formed by combining MTU1.TCNT and MTU2.TCNT.
Page 872 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.15 Timer General Register (TGR) (1) MTU0.TGR to MTU7.TGR Address(es): MTU0.TGRA H’0_1000_1308, MTU0.TGRB H’0_1000_130A, MTU0.TGRC H’0_1000_130C, MTU0.TGRD H’0_1000_130E, MTU0.TGRE H’0_1000_1320, MTU0.TGRF H’0_1000_1322, MTU1.TGRA H’0_1000_1388, MTU1.TGRB H’0_1000_138A, MTU2.TGRA H’0_1000_1408, MTU2.TGRB H’0_1000_140A, MTU3.TGRA H’0_1000_1218, MTU3.TGRB H’0_1000_121A, MTU3.TGRC H’0_1000_1224, MTU3.TGRD H’0_1000_1226, MTU3.TGRE H’0_1000_1272, MTU4.TGRA H’0_1000_121C, MTU4.TGRB H’0_1000_121E, MTU4.TGRC H’0_1000_1228, MTU4.TGRD H’0_1000_122A, MTU4.TGRE H’0_1000_1274, MTU4.TGRF H’0_1000_1276,...
Page 873 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU8.TGR Address(es): MTU8.TGRA H’0_1000_160C, MTU8.TGRB H’0_1000_1610, MTU8.TGRC H’0_1000_1614, MTU8.TGRD H’0_1000_1618 Initial Value Initial Value Note: TGR must not be accessed in 8 or 16 bits; it should be accessed in 32 bits. The MTU0.TGR to MTU7.TGR registers are 16-bit readable/writable registers;...
Page 874 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.16 Timer Longword General Registers (TGRALW and TGRBLW) Address(es): MTU1.TGRALW H’0_1000_13A4, MTU1.TGRBLW H’0_1000_13A8 Initial Value Initial Value Note: TGRALW and TGRBLW must not be accessed in 8 or 16 bits; they should be accessed in 32 bits. The TGRALW (TGRBLW) register is a 32-bit readable/writable register.
Page 875 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.17 Timer Start Registers (TSTRA, TSTRB, and TSTR) (1) MTU.TSTRA (MTU0, MTU1, MTU2, MTU3, MTU4, MTU8) Address(es): MTU.TSTRA H’0_1000_1280 CST4 CST3 — — CST8 CST2 CST1 CST0 Initial Value Initial Value Bit Name Description CST0...
Page 876 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU.TSTRB(MTU6, MTU7) Address(es): MTU.TSTRB H’0_1000_1A80 CST7 CST6 — — — — — — Initial Value Initial Bit Name Value Description b5 to b0 — All 0 Reserved These bits are read as 0. The write value should be 0. CST6 Counter Start 6 0: MTU6.TCNT counting is stopped...
Page 877 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (3) MTU5.TSTR(MTU5) Address(es): MTU5.TSTR H’0_1000_1CB4 — — — — — CSTU5 CSTV5 CSTW5 Initial Value Initial Bit Name Value Description CSTW5 Counter Start W5 0: MTU5.TCNTW counting is stopped 1: MTU5.TCNTW performs count operation CSTV5 Counter Start V5 0: MTU5.TCNTV counting is stopped...
Page 878 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.18 Timer Synchronous Registers (TSYRA and TSYRB) (1) MTU.TSYRA(MTU0, MTU1, MTU2, MTU3, MTU4) Address(es): MTU.TSYRA H’0_1000_1281 SYNC4 SYNC3 — — — SYNC2 SYNC1 SYNC0 Initial Value Initial Value Bit Name Description SYNC0 Timer Synchronous Operation 0 0: MTU0.TCNT operates independently...
Page 879 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU.TSYRB(MTU6, MTU7) Address(es): MTU.TSYRB H’0_1000_1A81 SYNC7 SYNC6 — — — — — — Initial Value Initial Bit Name Value Description b5 to b0 — All 0 Reserved These bits are read as 0. The write value should be 0. SYNC6 Timer Synchronous Operation 6 0: MTU6.TCNT operates independently...
Page 880 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.19 Timer Counter Synchronous Start Register (TCSYSTR) Address(es): MTU.TCSYSTR H’0_1000_1282 SCH0 SCH1 SCH2 SCH3 SCH4 — SCH6 SCH7 Initial Value R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial Bit Name Value Description SCH7...
Page 881 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) SCH4 Bit (Synchronous Start 4) This bit controls synchronous start of TCNT in MTU4. [Clearing condition] ● When the CST4 bit in TSTRA is set to 1 while SCH4 = 1 SCH3 Bit (Synchronous Start 3) This bit controls synchronous start of TCNT in MTU3.
Page 882 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.20 Timer Read/Write Enable Registers (TRWERA and TRWERB) Address(es): MTU.TRWERA H’0_1000_1284, MTU.TRWERB H’0_1000_1A84 — — — — — — — Initial Value Initial Bit Name Value Description Read/Write Enable 0: Read/write access to the registers is disabled 1: Read/write access to the registers is enabled b7 to b1 —...
Page 883 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.21 Timer Output Master Enable Registers (TOERA and TOERB) (1) MTU.TOERA Address(es): MTU.TOERA H’0_1000_120A — — OE4D OE4C OE3D OE4B OE4A OE3B Initial Value Initial Value Bit Name Description OE3B Master Enable MTIOC3B 0: MTU output is disabled* 1: MTU output is enabled OE4A...
Page 884 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU.TOERB Address(es): MTU.TOERB H’0_1000_1A0A — — OE7D OE7C OE6D OE7B OE7A OE6B Initial Value Initial Bit Name Value Description OE6B Master Enable MTIOC6B 0: MTU output is disabled* 1: MTU output is enabled OE7A Master Enable MTIOC7A 0: MTU output is disabled*...
Page 885 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.22 Timer Output Control Registers 1 (TOCR1A and TOCR1B) Address(es): MTU.TOCR1A H’0_1000_120E, MTU.TOCR1B H’0_1000_1A0E — PSYE — — TOCL TOCS OLSN OLSP Initial Value Initial Bit Name Value Description OLSP Output Level Select P* See Table 16.43.
Page 886 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) TOCL Bit (TOC Register Write Protection) This bit enables or disables write access to the TOCS, OLSN, and OLSP bits in TOCR1j (j = A, B). PSYE Bit (PWM Synchronous Output Enable) This bit enables or disables toggle output synchronized with the PWM cycle.
Page 887 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.23 Timer Output Control Registers 2 (TOCR2A and TOCR2B) Address(es): MTU.TOCR2A H’0_1000_120F, MTU.TOCR2B H’0_1000_1A0F BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Initial Value Initial Bit Name Value Description OLS1P Output Level Select 1P* This bit selects the output level on MTIOC3B or MTIOC6B in reset-synchronized PWM mode and complementary PWM mode.
Page 888 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.45 MTIOCmB Output Level Select Function Bit 0 Function Compare Match Output OLS1P Initial Output Active Level Up-Counting Down-Counting High level Low level Low level High level Low level High level High level Low level Note: m = 3, 6...
Page 889 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.50 MTIOCmD Output Level Select Function Bit 5 Function Compare Match Output OLS3N Initial Output Active Level Up-Counting Down-Counting High level Low level High level Low level Low level High level Low level High level Note: m = 4, 7...
Page 890 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.24 Timer Output Level Buffer Registers (TOLBRA and TOLBRB) Address(es): MTU.TOLBRA H’0_1000_1236, MTU.TOLBRB H’0_1000_1A36 — — OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Initial Value Initial Bit Name Value Description OLS1P Output Level Select 1P Specify the buffer value to be transferred to the OLS1P bit in TOCR2j.
Page 891 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.25 Timer Gate Control Register A (TGCRA) Address(es): MTU.TGCRA H’0_1000_120D — Initial Value Initial Bit Name Value Description Output Phase Switch These bits turn on or off the positive-phase/negative-phase output. The setting of these bits is valid only when the FB bit is set to 1.
Page 892 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) N Bit (Negative-Phase Output (N) Control) This bit selects the level output or the reset-synchronized PWM/complementary PWM output for the negative-phase output pins (MTIOC3D, MTIOC4C, and MTIOC4D pins). BDC Bit (Brushless DC Motor) This bit selects whether to make the functions of TGCRA effective or ineffective.
Page 893 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.26 Timer Subcounters (TCNTSA and TCNTSB) Address(es): MTU.TCNTSA H’0_1000_1220, MTU.TCNTSB H’0_1000_1A20 Initial Value Note: TCNTSA and TCNTSB must not be accessed in eight bits; it should be accessed in 16 bits. TCNTSA and TCNTSB are 16-bit read-only counters that are used only in complementary PWM mode.
Page 894 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.28 Timer Cycle Buffer Registers (TCBRA and TCBRB) Address(es): MTU.TCBRA H’0_1000_1222, MTU.TCBRB H’0_1000_1A22 Initial Value Note: TCBRA and TCBRB must not be accessed in eight bits; it should be accessed in 16 bits. TCBRA and TCBRB are 16-bit readable/writable registers, used only in complementary PWM mode, that function as buffer registers for TCDRA and TCDRB.
Page 895 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.30 Timer Dead Time Enable Registers (TDERA and TDERB) Address(es): MTU.TDERA H’0_1000_1234, MTU.TDERB H’0_1000_1A34 — — — — — — — TDER Initial Value R/(W) Initial Bit Name Value Description TDER R/(W) Dead Time Enable 0: No dead time is generated 1: Dead time is generated*...
Page 896 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.31 Timer Buffer Transfer Set Registers (TBTERA and TBTERB) Address(es): MTU.TBTERA H’0_1000_1232, MTU.TBTERB H’0_1000_1A32 — — — — — — BTE[1:0] Initial Value Initial Bit Name Value Description b1, b0 BTE[1:0] All 0 Buffer Transfer Disable and Interrupt Skipping Link Setting These bits enable or disable transfer from the buffer registers*...
Page 897 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.32 Timer Waveform Control Registers (TWCRA and TWCRB) Address(es): MTU.TWCRA H’0_1000_1260, MTU.TWCRB H’0_1000_1A60 — — — — — Initial Value R/(W) R/(W) R/(W)* Initial Bit Name Value Description R/(W) Waveform Retain Enable 0: Initial values specified in TOCR1A and TOCR2A (TOCR1B and TOCR2B) are output 1: Initial output is inhibited...
Page 898 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) SCC Bit (Synchronous Clearing Control) The setting of this bit selects whether MTU6.TCNT and MTU7.TCNT are or are not cleared when counter-synchronous clearing is generated for MTU0, MTU1, MTU2–MTU6, MTU7 in complementary PWM mode. Make the complementary PWM mode settings for MTU6 and MTU7 when this function is in use.
Page 899 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.33 Noise Filter Control Register n (NFCRn) (n = 0 to 4, 6, 7, 8, C) (1) MTU0.NFCR0, MTU1.NFCR1, MTU2.NFCR2, MTU3.NFCR3, MTU4.NFCR4, MTU6.NFCR6, MTU7.NFCR7, MTU8.NFCR8 Address(es): MTU0.NFCR0 H’0_1000_1290, MTU1.NFCR1 H’0_1000_1291, MTU2.NFCR2 H’0_1000_1292, MTU3.NFCR3 H’0_1000_1293, MTU4.NFCR4 H’0_1000_1294, MTU6.NFCR6 H’0_1000_1A93, MTU7.NFCR7 H’0_1000_1A94, MTU8.NFCR8 H’0_1000_1298 —...
Page 900 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) NFBEN Bit (Noise Filter B Enable) This bit disables or enables the noise filter for input from the MTIOCnB pin. Since changing the value of the bit may lead to the internal generation of an unexpected edge, select the output compare function for the relevant pin in the timer I/O control register or set the TMDR.MD[3:0] bits to a value other than that for normal mode (0000b) before doing so.
Page 901 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU0.NFCRC Address(es): MTU0.NFCRC H’0_1000_1299 — — NFCS[1:0] NFDEN NFCEN NFBEN NFAEN Initial Value Initial Bit Name Value Description NFAEN Noise Filter A Enable 0: The noise filter for the MTCLKA pin is disabled. 1: The noise filter for the MTCLKA pin is enabled.
Page 902 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) NFDEN Bit (Noise Filter D Enable) This bit disables or enables the noise filter for input from the MTCLKD pin. Since changing the value of the bit may lead to the internal generation of an unexpected edge, do so after stopping the internal counter. NFCS[1:0] Bits (Noise Filter Clock Select) These bits set the sampling interval for the noise filters.
Page 903 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.34 Noise Filter Control Register 5 (NFCR5) Address(es): MTU5.NFCR5 H’0_1000_1A95 — — NFCS[1:0] — NFWEN NFVEN NFUEN Initial Value Initial Bit Name Value Description NFUEN Noise Filter U Enable 0: The noise filter for the MTIC5U pin is disabled. 1: The noise filter for the MTIC5U pin is enabled.
Page 904 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.35 Timer A/D Converter Start Request Control Register (TADCR) (1) MTU4.TADCR Address(es): MTU4.TADCR H’0_1000_1240 BF[1:0] — — — — — — UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Initial Value Initial Value Bit Name...
Page 905 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Initial Bit Name Value Description b15, b14 BF[1:0] All 0 MTU4.TADCOBRA/TADCOBRB Transfer Timing Select See Table 16.54 for details. These bits specify the transfer timing from MTU4.TADCOBRA and MTU4.TADCOBRB to MTU4.TADCORA and MTU4.TADCORB. Note: The TADCR register in MTU4 must not be accessed in eight bits;...
Page 906 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU7.TADCR Address(es): MTU7.TADCR H’0_1000_1A40 BF[1:0] — — — — — — UT7AE DT7AE UT7BE DT7BE ITA6AE ITA7VE ITB6AE ITB7VE Initial Value Initial Bit Name Value Description ITB7VE TCIV7 Interrupt Skipping Link Enable* 0: A/D converter start request signal TRG7BN and TCIV7 interrupt skipping 1 are not linked 1: A/D converter start request signal TRG7BN and TCIV7 interrupt skipping 1 are...
Page 907 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Initial Bit Name Value Description b15, b14 BF[1:0] All 0 MTU7.TADCOBRA/TADCOBRB Transfer Timing Select See Table 16.55 for details. These bits specify the transfer timing from MTU7.TADCOBRA and MTU7.TADCOBRB to MTU7.TADCORA and MTU7.TADCORB. Note: The TADCR register in MTU7 must not be accessed in eight bits;...
Page 908 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.36 Timer A/D Converter Start Request Cycle Set Registers (TADCORA and TADCORB) Address(es): MTU4.TADCORA H’0_1000_1244, MTU4.TADCORB H’0_1000_1246, MTU7.TADCORA H’0_1000_1A44, MTU7.TADCORB H’0_1000_1A46 Initial Value Note: TADCORA and TADCORB must not be accessed in eight bits; it should be accessed in 16 bits. Note 1.
Page 909 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.37 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA and TADCOBRB) Address(es): MTU4.TADCOBRA H’0_1000_1248, MTU4.TADCOBRB H’0_1000_124A, MTU7.TADCOBRA H’0_1000_1A48, MTU7.TADCOBRB H’0_1000_1A4A Initial Value Note: TADCOBRA and TADCOBRB must not be accessed in eight bits; it should be accessed in 16 bits. TADCOBRA and TADCOBRB are 16-bit readable/writable registers whose values are transferred to TADCORA and TADCORB, respectively, when the crest or trough of the MTUn.TCNT count is reached.
Page 910 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.39 Timer Interrupt Skipping Set Registers 1 (TITCR1A and TITCR1B) (1) MTU.TITCR1A Address(es): MTU.TITMRA H’0_1000_1230 T3AEN T3ACOR[2:0] T4VEN T4VCOR[2:0] Initial Value Initial Value Bit Name Description b2 to b0 T4VCOR[2:0] All 0 TCIV4 Interrupt Skipping Count Setting These bits specify the TCIV4 interrupt skipping count within the range from 0 to 7.* For details, see Table 16.56.
Page 911 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU.TITCR1B Address(es): MTU.TITCR1B H’0_1000_1A30 T6AEN T6ACOR[2:0] T7VEN T7VCOR[2:0] Initial Value Initial Bit Name Value Description b2 to b0 T7VCOR[2:0] All 0 TCIV7 Interrupt Skipping Count Setting These bits specify the TCIV7 interrupt skipping count within the range from 0 to 7.* For details, see Table 16.58.
Page 912 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.57 Setting of Interrupt Skipping Count by T3ACOR[2:0] Bits Bit 6 Bit 5 Bit 4 T3ACOR2 T3ACOR1 T3ACOR0 Description Does not skip TGIA3 interrupts. Sets the TGIA3 interrupt skipping count to 1. Sets the TGIA3 interrupt skipping count to 2.
Page 913 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.40 Timer Interrupt Skipping Counters 1 (TITCNT1A and TITCNT1B) (1) MTU.TITCNT1A Address(es): MTU.TITCNT1A H’0_1000_1231 — T3ACNT[2:0] — T4VCNT[2:0] Initial Value Initial Value Bit Name Description b2 to b0 T4VCNT[2:0] All 0 TCIV4 Interrupt Counter While the T4VEN bit in TITCR1A is set to 1, the count in these bits is incremented every time a TCIV4 interrupt occurs.
Page 914 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU.TITCNT1B Address(es): MTU.TITCNT1B H’0_1000_1A31 — T6ACNT[2:0] — T7VCNT[2:0] Initial Value Initial Bit Name Value Description b2 to b0 T7VCNT[2:0] All 0 TCIV7 Interrupt Counter While the T7VEN bit in TITCR1B is set to 1, the count in these bits is incremented every time a TCIV7 interrupt occurs.
Page 915 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.41 Timer Interrupt Skipping Set Registers 2 (TITCR2A and TITCR2B) (1) MTU.TITCR2A Address(es): MTU.TITCR2A H’0_1000_123B — — — — — TRG4COR[2:0] Initial Value Initial Value Bit Name Description b2 to b0 TRG4COR All 0 TRG4AN/TRG4BN Interrupt Skipping Count Setting...
Page 916 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU.TITCR2B Address(es): MTU.TITCR2B H’0_1000_1A3B — — — — — TRG7COR[2:0] Initial Value Initial Bit Name Value Description b2 to b0 TRG7COR All 0 TRG7AN/TRG7BN Interrupt Skipping Count Setting [2:0] These bits specify the TRG7AN/TRG7BN interrupt skipping count within the range from 0 to 7.
Page 917 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.42 Timer Interrupt Skipping Counters 2 (TITCNT2A and TITCNT2B) (1) MTU.TITCNT2A Address(es): MTU.TITCNT2A H’0_1000_123C — — — — — TRG4CNT[2:0] Initial Value Initial Value Bit Name Description b2 to b0 TRG4CNT All 0 TRG4AN/TRG4BN Interrupt Counter [2:0]...
Page 918 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) MTU.TITCNT2B Address(es): MTU.TITCNT2B H’0_1000_1A3C — — — — — TRG7CNT[2:0] Initial Value Initial Bit Name Value Description b2 to b0 TRG7CNT All 0 TRG7AN/TRG7BN Interrupt Counter [2:0] These bits start counting from the value set in TRG7COR[2:0] and the count decrements every time TRG7AN or TRG7BN is generated.
Page 919 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.2.43 Bus Master Interface The timer counter (MTU8.TCNT), general registers (MTU8.TGRn) for MTU8, and MTU1.TCNTLW, MTU1.TGRALW, and MTU1.TGRBLW registers when TMDR3.LWA = 1 are 32-bit registers. A 32-bit data bus to the bus master enables 32-bit read/write access.
Page 920 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.3 Operation 16.3.1 Basic Functions Each channel has TCNT and TGR. TCNT in each channel performs up-counting and is also capable of free-running count, periodic count, and external event count operations. Each TGR can be used as an input capture register or an output compare register.
Page 921 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (b) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, all TCNT counters are designated as free-running counters. When the CSTn bit in TSTRA, TSTRB, or TSTR in MTU5 is set to 1, the corresponding TCNT counter starts up-counting as a free-running counter. When TCNT overflows (from H’FFFF to H’0000), if the corresponding TIER.TCIEV bit is 1, an interrupt request is issued to the CPU.
Page 922 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) Waveform Output by Compare Match Upon compare match, low, high, or toggle output from the corresponding pin can be performed. The compare match output operation is not available in MTU5. (a) Example of Procedure for Setting Waveform Output by Compare Match Figure 16.8 shows an example of the procedure for setting waveform output by compare match Output selection...
Page 923 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (b) Examples of Waveform Output Operation Figure 16.9 shows an example of low output and high output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that high is output by compare match A and low is output by compare match B.
Page 924 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the MTIOCnm, MTIC5U, MTIC5V, or MTIC5W pin (n = 0 to 4, 6, 7, 8; m = A to D), input edge. The rising edge, falling edge, or both edges can be selected as the detection edge.
Page 925 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (b) Example of Input Capture Operation Figure 16.12 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the MTIOCnA pin input capture input edge, the falling edge has been selected as the MTIOCnB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 926 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.3.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be modified simultaneously (synchronous setting). In addition, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR.
Page 927 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) Example of Synchronous Operation Figure 16.14 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for MTU0 to MTU 2, MTU0.TGRB compare match has been set as the counter clearing source in MTU0, and synchronous clearing has been set for the counter clearing source in MTU1 and MTU2.
Page 928 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.3.3 Buffer Operation Buffer operation, provided for MTU0, MTU3, MTU4, MTU6, MTU7, and MTU8, enables TGRC and TGRD to be used as buffer registers. In MTU0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 929 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) When TGR is an input capture register When an input capture occurs, the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register. This operation is illustrated in Figure 16.16.
Page 930 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) Examples of Buffer Operation (a) When TGR is an Output Compare Register Figure 16.18 shows an operation example in which PWM mode 1 has been designated for MTU0, and buffer operation has been designated for TGRA and TGRC.
Page 931 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (b) When TGR is an Input Capture Register Figure 16.19 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the MTIOCnA pin input capture input edge.
Page 932 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for MTU0 or in PWM mode 1 for MTU3, MTU4, MTU6, and MTU7 by setting the buffer operation transfer mode registers (MTUn.TBTM (n = 0, 3, 4, 6, 7)).
Page 933 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.3.4 Cascaded Operation In cascaded operation, two 16-bit counters in different channels are used together as a 32-bit counter. There are two functions for connecting MTU1 and MTU2 to use as a 32-bit counter: cascade connection to be set when the MTU1.TMDR3.LWA bit is 0, and cascade connection 32-bit phase counting mode to be set when the MTU1.TMDR3.LWA bit is 1.
Page 934 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (1) Example of Cascaded Operation Setting Procedure Figure 16.21 shows an example of the cascaded operation setting procedure. Cascaded operation [1] Set the TPSC[2:0] bits in TCR to 111b in MTU1 to select Set cascading counting at a TCNT overflow/underflow in MTU2.
Page 935 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (3) Cascaded Operation Example (b) Figure 16.23 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the I2AE bit in TICCR has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the MTU1.TIOR.IOA[3:0] bits have selected the MTIOC1A rising edge for the input capture timing while the MTU2.TIOR.IOA[3:0] bits have selected the MTIOC2A rising edge for the input capture timing.
Page 936 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (4) Cascaded Operation Example (c) Figure 16.24 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE and I1AE bits have been set to 1 to include the MTIOC2A and MTIOC1A pins in the MTU1.TGRA and MTU2.TGRA input capture conditions, respectively.
Page 937 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (5) Cascaded Operation Example (d) Figure 16.25 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE bit has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the IOA[3:0] bits in MTU1.TIOR have selected occurrence of MTU0.TGRA compare match or input capture for the input capture timing while the IOA[3:0] bits in MTU2.TIOR have selected the MTIOC2A rising edge for the input capture timing.
Page 938 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.3.5 PWM Modes PWM modes are provided to output PWM waveforms from the external pins. The output level can be selected as low, high, or toggle output in response to a compare match of each TGR. PWM waveforms in the range of 0% to 100% duty cycle can be output according to the TGR settings.
Page 939 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.65 PWM Output Registers and Output Pins Output Pins Channel Register PWM Mode 1 PWM Mode 2 MTU0 TGRA MTIOC0A MTIOC0A TGRB MTIOC0B TGRC MTIOC0C MTIOC0C TGRD MTIOC0D MTU1 TGRA MTIOC1A MTIOC1A TGRB...
Page 940 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (1) Example of PWM Mode Setting Procedure Figure 16.26 shows an example of the PWM mode setting procedure. PWM mode [1] Enable TOERA output when outputting a waveform from the Enable waveform output MTIOC pin of MTU3 and MTU4.
Page 941 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) Examples of PWM Mode Operation Figure 16.27 shows an example of operation in PWM mode 1. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set as the initial output value and output value for TGRA, and 1 is set as the output value for TGRB.
Page 942 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Figure 16.29 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode 1. In these examples, TGRA compare match is selected as the TCNT clearing source, the initial output value and the output value for TGRA are set to the low level, and the output value for TGRB is set to the high level.
Page 943 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.3.6 Phase Counting Mode There are two phase counting modes: 16-bit phase counting mode in which MTU1 and MTU2 operate independently, and cascade connection 32-bit phase counting mode in which MTU1 and MTU2 are cascaded. In phase counting mode, the phase difference between two external input clocks is detected and the corresponding TCNT is incremented or decremented.
Page 944 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.3.6.1 16-Bit Phase Counting Mode When the MTU1.TMDR3.LWA is 0, 16-bit phase counting mode can be set individually for MTU1 and MTU2. In 16-bit phase counting mode, the phase difference between two external input clocks is detected and the 16-bit counter TCNT of the corresponding channel is incremented or decremented.
Page 945 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) Examples of 16-Bit Phase Counting Mode Operation In phase counting mode, TCNT is incremented or decremented according to the phase difference between two external clocks. There are five modes according to the count conditions. Each mode operates under the condition PHCKSEL = 1, which means the phase clock for MTU1 is input from MTCLKA or MTCLKB and that for MTU2 is input from MTCLKC or MTCLKD.
Page 946 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (b) Phase Counting Mode 2 Figure 16.32 to Figure 16.34 show the examples of operation in phase counting mode 2 and Table 16.68 summarizes the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2)
Page 947 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Up-counting Down-counting Time Figure 16.34 Example of Operation in Phase Counting Mode 2 (When MTUn.TCR2.PCB[1:0] is 1xb (n = 1, 2)) Table 16.68 Up-Counting and Down-Counting Conditions in Phase Counting Mode 2 MTCLKA (MTU1)
Page 948 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (c) Phase Counting Mode 3 Figure 16.35 to Figure 16.37 show the examples of operation in phase counting mode 3 and Table 16.69 summarizes the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2)
Page 949 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Down-counting Up-counting Time Figure 16.37 Example of Operation in Phase Counting Mode 3 (When MTUn.TCR2.PCB[1:0] is 1xb (n = 1, 2)) R01UH1014EJ0110 Rev.1.10 Page 949 of 3776...
Page 950 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.69 Up-Counting and Down-Counting Conditions in Phase Counting Mode 3 MTCLKA (MTU1) MTCLKB (MTU1) PCB[1:0] MTCLKC (MTU2) MTCLKD (MTU2) Operation High Not counted (Don’t care) High Up-counting High Down-counting Not counted (Don’t care) High High Down-counting...
Page 951 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (d) Phase Counting Mode 4 Figure 16.38 shows an example of operation in phase counting mode 4, and Table 16.70 summarizes the TCNT up- counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value...
Page 952 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (e) Phase Counting Mode 5 Figure 16.39 and Figure 16.40 show the examples of operation in phase counting mode 5 and Table 16.71 summarizes the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2)
Page 953 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.71 Up-Counting and Down-Counting Conditions in Phase Counting Mode 5 MTCLKA (MTU1) MTCLKB (MTU1) PCB[1:0] MTCLKC (MTU2) MTCLKD (MTU2) Operation High Not counted (Don’t care) High Up-counting High Not counted (Don’t care) High Up-counting High...
Page 954 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (3) 16-Bit Phase Counting Mode Application Example Figure 16.41 shows an example in which MTU1 is in phase counting mode, and MTU1 is coupled with MTU0 to input 2-phase encoder pulses of a servo motor in order to detect position or speed. MTU1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to MTCLKA and MTCLKB.
Page 955 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.3.6.2 Cascade Connection 32-Bit Phase Counting Mode When MTU1 is set to phase counting mode by setting MTU1.TMDR3.LWA = 1, MTU1 and MTU2 are connected to operate in cascade connection 32-bit phase counting mode as shown in Figure 16.42. When this mode is used, the TCR, TCR2, TIOR, TIER, TGR, and TSR registers are controlled by MTU1 and the settings of MTU2 are disabled.
Page 956 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) A-phase signal MTCLKA MTU1 and MTU2 Count clock B-phase signal Edge detection logic Value to be counted 32-bit up/down-counter MTCLKB (TCNTLW) Clear the counter Z-phase signal 32-bit general register_A (TGRALW) Capture 32-bit general register_B (TGRBLW) MTIOC1A...
Page 957 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (1) Example of Setting Cascade Connection 32-Bit Phase Counting Mode Figure 16.43 shows an example of the procedure for setting cascade connection 32-bit phase counting mode. 32-bit Phase Counting Mode [1] Set the LWA bit in MTU1.TMDR3 to 1 and combine MTU1 and MTU3 for Combine MTU1 and MTU2 for access as a 32-bit unit.* access as a 32-bit unit.
Page 958 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.3.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three phases of positive and negative PWM waveforms (six phases in total) that share a common wave transition point can be output by combining MTU3 and MTU4 and MTU6 and MTU7. When set for reset-synchronized PWM mode, the MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, MTIOC4D, MTIOC6B, MTIOC6D, MTIOC7A, MTIOC7C, MTIOC7B, and MTIOC7D pins function as PWM output pins and timer counters 6 and 12 (MTU3.TCNT and MTU6.TCNT) functions as an up-counter.
Page 959 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (1) Example of Procedure for Setting Reset-Synchronized PWM Mode Figure 16.44 shows an example of the procedure for specifying the reset-synchronized PWM mode. Reset-synchronized PWM mode [1] Clear the TSTRA.CST3 (TSTRB.CST6) and TSTRA.CST4 (TSTRB.CST7) Stop counting bits to 0 to stop the TCNT count operation.
Page 960 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) Example of Reset-Synchronized PWM Mode Operation Figure 16.45 shows an example of operation in the reset-synchronized PWM mode. MTU3.TCNT and MTU4.TCNT (MTU6.TCNT and MTU7.TCNT) operate as up-counters. The counters are cleared when a compare match occurs between MTU3.TCNT (MTU6.TCNT) and MTU3.TGRA (MTU6.TGRA), and then begin incrementing from H’0000.
Page 961 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) 16.3.8 Complementary PWM Mode In complementary PWM mode, dead time can be set for PWM waveforms to be output. The dead time is the period during which the upper and lower arm transistors are set to the inactive level in order to prevent short-circuiting of the arms.
Page 962 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.75 Register Settings for Complementary PWM Mode (1/2) Counter / Channel Register Description Read/Write from CPU MTU3 TCNT Starts up-counting from the value set in the dead time register Maskable by TRWERA setting* TGRA Set MTU3.TCNT upper limit value (1/2 carrier cycle + dead time) Maskable by TRWERA setting*...
Page 963 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Table 16.76 Register Settings for Complementary PWM Mode (2/2) Counter / Register Description Read/Write from CPU Timer dead time data register A (TDDRA) Set MTU4.TCNT and MTU3.TCNT offset value Maskable by TRWERA setting* (dead time value) Timer dead time data register B (TDDRB) Set MTU7.TCNT and MTU6.TCNT offset value...
Page 964 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) MTU3.TGRC TCBRA TDDRA MTU3.TGRA TCDRA MTIOC3A Comparator Match signal MTIOC3B MTIOC3D MTU3.TCNT TCNTSA MTU4.TCNT MTIOC4A MTIOC4B MTIOC4C Comparator MTIOC4D Match signal External cutoff input MTU3.TGRB MTU4.TGRA MTU4.TGRB POE0# POE4# POE8# POE10# External cutoff interrupt : Registers that can be read or written from the CPU : Registers that can be read or written from the CPU...
Page 965 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) MTU6.TGRC TCBRB TDDRB MTU6.TGRA TCDRB MTIOC6A Comparator Match signal MTIOC6B MTIOC6D MTU6.TCNT TCNTSB MTU7.TCNT MTIOC7A MTIOC7B MTIOC7C Comparator MTIOC7D Match signal External cutoff input MTU6.TGRB MTU7.TGRA MTU7.TGRB POE0# POE4# POE8# POE10# External cutoff interrupt : Registers that can be read or written from the CPU : Registers that can be read or written from the CPU...
Page 966 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (1) Example of Complementary PWM Mode Setting Procedure Figure 16.48 shows an example of the complementary PWM mode setting procedure. [1] Clear the TSTRA.CST3 (TSTRB.CST6) and TSTRA.CST4 (TSTRB.CST7) bits to 0 to Complementary PWM mode stop the TCNT count operation.
Page 967 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (2) Outline of Complementary PWM Mode Operation In complementary PWM mode, six phases (three positive and three negative) PWM waveforms can be output. Figure 16.49 illustrates counter operation in complementary PWM mode (MTU3 and MTU4), and Figure 16.50 shows an example of operation in complementary PWM mode.
Page 968 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (b) Register Operation In complementary PWM mode, nine registers (compare registers, buffer registers, and temporary registers) are used to control the duty ratio for the PWM output. Figure 16.50 shows an example of operation in complementary PWM mode (MTU3 and MTU4).
Page 969 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) Transfer from temporary register Transfer from temporary register MTU3.TCNT to compare register to compare register MTU4.TCNT TCNTSA MTU3.TGRA TCNTSA TCDRA MTU3.TCNT MTU4.TGRA MTU4.TCNT MTU4.TGRC TDDRA H’0000 Buffer register H’6400 H’0080 MTU4.TGRC Temporary register H’6400 H’0080...
Page 970 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (c) Initial Setting In complementary PWM mode, there are nine registers that require initial setting. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with MTU3.TMDR1.MD[3:0] (MTU6.TMDR1.MD[3:0]) bits, initial values should be set in the following registers.
Page 971 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (d) PWM Output Level Setting In complementary PWM mode, the PWM output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1A or TOCR1B) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2A or TOCR2B).
Page 972 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (f) Dead Time Suppressing Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable register (TDERA or TDERB) to 0. TDERA (TDERB) can be cleared to 0 only when 0 is written to it after reading TDER = 1. MTU3.TGRA and MTU4.TGRC (MTU6.TGRA and MTU7.TGRC) should be set to 1/2 PWM cycle + 1 and the timer dead time data register (TDDRA or TDDRB) should be set to 1.
Page 973 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (g) PWM Cycle Setting In complementary PWM mode, the PWM cycle is set in two registers—MTU3.TGRA (MTU6.TGRA), in which the MTU3.TCNT (MTU6.TCNT) upper limit value is set, and TCDRA (TCDRB), in which the MTU4.TCNT (MTU7.TCNT) upper limit value is set.
Page 974 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (h) Register Data Updating In complementary PWM mode, buffer registers are used to update the data in five compare registers for PWM duty and PWM cycle. The update data can be written to the buffer registers at any time. There is a temporary register between each of these registers and its buffer register.
Page 975 RZ/G3S Group 16 Multi-Function Timer Pulse Unit 3 (MTU3a) : Compare register l Data update timing: counter crest and trough : Buffer register Transfer from Transfer from Transfer from Transfer from Transfer from Transfer from temporary register temporary register temporary register temporary register temporary register temporary register...
Page 976 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (i) Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of the OLSN and OLSP bits in the TOCR1A (TOCR1B) register or the OLS1N to OLS3N and OLS1P to OLS3P bits in the TOCR2A register (TOCR2B).
Page 977 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) l Timer output control register settings TOCR1A.OLSN bit = 0 (initial output: high; active level: low) TOCR1A.OLSP bit = 0 (initial output: high; active level: low) MTU3.TCNT MTU3.TCNT MTU4.TCNT MTU4.TCNT value TCNTSA MTU3.TCNT MTU4.TCNT...
Page 978 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (j) Method for Generating PWM Output in Complementary PWM Mode In complementary PWM mode, six phases (three positive and three negative) PWM waveforms can be output. Dead time can be set for PWM waveforms to be output. A PWM waveform is generated by output of the level selected in the timer output control register in the event of a compare match between a counter and a compare register.
Page 979 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) T1 interval T2 interval T1 interval Counter for generating a turn-off timing MTU3.TGRA Counter for generating a turn-on timing TEMP2 TCDRA MTU4.TGRA a’ b’ TDDRA H’0000 Positive-phase output Negative-phase output Output waveform is active-low. Buffer operation is set to transfer at the crest and trough.
Page 980 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) T1 interval T2 interval T1 interval MTU3.TGRA Counter for generating a turn-off timing Counter for generating a turn-on timing TCDRA MTU4.TGRA TDDRA TEMP2 a’ b’ H’0000 Positive-phase output Negative-phase Don’t care output Output waveform is active-low.
Page 981 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (k) 0% and 100% Duty Ratio Output in Complementary PWM Mode In complementary PWM mode, 0% and 100% duty PWM output can be output as required. Figure 16.59 to Figure 16.63 show output examples. A 100% duty waveform is output when the compare register value is set to H’0000.
Page 982 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) T1 interval T2 interval T1 interval MTU3.TGRA Counter for generating a turn-off timing Counter for generating a turn-on timing TCDRA MTU4.TGRA TDDRA TEMP2 H’0000 100% duty ratio output Positive-phase output Don’t care Negative-phase 0% duty ratio output output...
Page 983 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) T1 interval T2 interval T1 interval MTU3.TGRA Counter for generating a turn-off timing Counter for generating a turn-on timing TCDRA MTU4.TGRA TDDRA TEMP2 H’0000 a’ c b’ 100% duty ratio output Positive-phase output Don’t care...
Page 984 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (l) Toggle Output Synchronized with PWM Cycle In complementary PWM mode, toggle output from the PWM output pin in synchronization with the PWM cycle can be enabled by setting the PSYE bit in the TOCR1A (TOCR1B) register to 1. An example of a toggle output waveform is shown in Figure 16.64.
Page 985 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (m) Counter Clearing by Another Channel In complementary PWM mode, MTU3.TCNT, MTU4.TCNT, and TCNTSA (MTU6.TCNT, MTU7.TCNT, and TCNTSB) can be cleared by another channel source when a mode for synchronization with another channel is specified through the TSYRA (TSYRB) register and synchronous clearing is selected with MTU3.TCR.CCLR[2:0] (MTU6.TCR.CCLR[2:0]) bits.
Page 986 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCRA (TWCRB) to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval (Tb2 interval) at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing.
Page 987 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) ● Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode. An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in Figure 16.67.
Page 988 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) ● Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figure 16.68 to Figure 16.71 show examples of output waveform control in which MTU3 and MTU4 operate in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCRA is set to 1.
Page 989 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) MTU3.TCNT MTU4.TCNT Synchronous TCNTSA clearing WRE bit = 1 MTU3.TGRA TCDRA MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDRA H’0000 Positive-phase output Negative-phase output (Output waveform is active-low) Figure 16.69 Example of Synchronous Clearing in Tb1 interval (Timing (6) in Figure 16.66;...
Page 990 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) MTU3.TCNT MTU4.TCNT Synchronous TCNTSA WRE bit = 1 clearing MTU3.TGRA TCDRA MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDRA H’0000 Positive-phase output Initial value output is suppressed Negative-phase output (Output waveform is active-low) Figure 16.71 Example of Synchronous Clearing in Tb2 interval (Timing (11) in Figure 16.66;...
Page 991 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (o) Suppressing Synchronous Counter Clearing for MTU0 to MTU2 and MTU6 and MTU7 In MTU6 and MTU7, setting the SCC bit in TWCRB to 1 suppresses synchronous counter clearing caused by MTU0 to MTU2.
Page 992 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) ● Example of Procedure for Suppressing Synchronous Counter Clearing for MTU0 to MTU2, and MTU6 and MTU7 An example of the procedure for suppressing synchronous counter clearing for MTU0 to MTU2, and MTU6 and MTU7 is shown in Figure 16.73.
Page 993 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) ● Examples of Suppression of Synchronous Counter Clearing for MTU 0 to MTU2, and MTU6 and MTU7 Figure 16.74 to Figure 16.77 show examples of operation in which MTU6 and MTU7 operate in complementary PWM mode and synchronous counter clearing for MTU 0 to MTU2, and MTU6 and MTU7 is suppressed by setting the SCC bit in TWCRB in MTU6 and MTU7 to 1.
Page 994 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) MTU6.TCNT MTU7.TCNT WRE bit = 1 Synchronous clearing for TCNTSA SCC bit = 1 MTU0 to MTU2 and MTU6 and MTU7 MTU6.TGRA TCDRB MTU6.TGRB MTU6.TCNT MTU7.TCNT Counters are not cleared TDDRB H’0000 Positive-phase output...
Page 995 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) MTU6.TCNT MTU7.TCNT WRE bit = 1 Synchronous clearing for TCNTSA SCC bit = 1 MTU0 to MTU2 and MTU6 and MTU7 MTU6.TGRA TCDRB MTU6.TGRB MTU6.TCNT MTU7.TCNT Counters are cleared TDDRB H’0000 Positive-phase output Negative-phase...
Page 996 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (p) Counter Clearing by MTU3.TGRA (MTU6.TGRA) Compare Match In complementary PWM mode, MTU3.TCNT, MTU4.TCNT, and TCNTSA (MTU6.TCNT, MTU7.TCNT, and TCNTSB) can be cleared by MTU3.TGRA (MTU6.TGRA) compare match when the TWCRA.CCE (TWCRB.CCE) bit.
Page 997 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (q) Example of Waveform Output for Driving AC Synchronous Motor (Brushless DC Motor) In complementary PWM mode when MTU3 and MTU4 are used, a brushless DC motor can easily be controlled using TGCRA.
Page 998 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) l When TGCRA.BDC = 1, TGCRA.N = 1, TGCRA.P = 1, TGCRA.FB = 0, and output active level = high External input MTIOC0A pin MTIOC0B pin MTIOC0C pin 6-phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin...
Page 999 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) l When TGCRA.BDC = 1, TGCRA.N = 1, TGCRA.P = 1, TGCRA.FB = 1, and output active level = high TGCRA UF bit VF bit WF bit 6-phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin...
Page 1000 RZ/G3S Group 16. Multi-Function Timer Pulse Unit 3 (MTU3a) (s) Double Buffer Function in Complementary PWM Mode In complementary PWM mode 3 (transfer at the crest and trough), the PWM output setting resolution can be improved from ±2 to ±1 by setting the TMDR2A.DRS (TMDR2B.DRS) bit to 1. When setting buffer registers A (TGRD in MTU3, TGRC and TGRD in MTU4, TGRD in MTU6, and TGRC and TGRD in MTU7), set also buffer registers B (TGRE in MTU3, TGRE and TGRF in MTU4, TGRE in MTU6, and TGRE and TGRF in MTU7) at the same time.

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Rz/g3s series