Location Monitor Fifo; Darf64 Vme Event; Timer Event; Figure 12: Timer Block Diagram - Performance Computer PT-VME151A User Manual

"vectored" for the EPAK and DUART interfaces. The vector is supplied by the interrupting
device, not the AVICS 64, during the interrupt acknowledge cycle.

Location Monitor FIFO

This interrupt indicates that there are entries in the DARF64 Location Monitor FIFO. It will
remain active until the FIFO becomes empty.
The interrupt is enabled by setting the L0E bit in the ACC Local Interrupt Enable Register.
The current state of this signal can be read in the LI0 status bit of the ACC Local Interrupt
Status Register. The interrupt request level presented to the 68040 is determined by 0L2,
0L1, and 0L0 control bits in the ACC Local Interrupts 1 and 0 Control Register. The
DARF64 -LMINT output drives the ACC interrupt input pin -LIRQ0 through signal line [-
INTP<0>].

DARF64 VME Event

This interrupt indicates that an event related to VMEbus use has occurred - such as DMA
has finished or a bus error (DARF64 [-KBER] or VMEbus [BERR*]) has occurred. It is
negated when the appropriate flags in the DARF64 status register are cleared.
The interrupt is enabled by setting the L1E bit in the ACC Local Interrupt Enable Register.
The current state of this signal can be read in the LI1 status bit of the ACC Local Interrupt
Status Register. The interrupt request level presented to the 68040 is determined by 1L2,
1L1, and 1L0 control bits in the ACC Local Interrupts 1 and 0 Control Register. The
DARF64 -VMEINT output drives the ACC interrupt input pin -LIRQ1 through signal line
[-INTP<1>].

Timer Event

The outputs of the Tick Timer and three Interval Timers are OR'ed together generating a
single interrupt to the CPU. This interrupt indicates that a Timer period has expired.
The Timer Event interrupt is enabled by setting the L2E bit in the ACC Local Interrupt
Enable Register. The current state of this signal can be read in the LI2 status bit of the ACC
Local Interrupt Status Register. The interrupt request level presented to the 68040 is deter-
mined by 2L2, 2L1, and 2L0 control bits in the ACC Local Interrupts 3 and 2 Control
Register.

Figure 12: Timer Block Diagram

System Control
Register 2
EITI Interval Timers
ETTI
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Interval Timer
Interrupt Request
Tick Timer
Interrupt Request
Extensible Single Board Computer/Controller User's Manual 41
Performance Computer
ACC
Timer Event
LIRQ2
TICK