Performance Computer PT-VME151A User Manual page 125

8
Section INDEX
D
D64MBLT
33
description
DARF
VMEbus Slave Base Address Register
47, 58
A32SIZ
59, 70
DARF64
91
68040 considerations
Access Protect Boundary Register
35
address modifiers
95, 98, 103
BI-mode
Control and Status Register
99, 103
BARDY
106
DLBER
106
DMAGO
106
DONE
38, 99, 100, 106
LBERR
96
LMHD
99, 106
VBERR
33, 99
decoupled mode
36
DMA
36
performance
DMA Local Address Register
DMA Transfer Count Register
DMA VMEbus Address Register
37
location monitor
Location Monitor FIFO Read Port
102
Memory Map Pages
37
message FIFO
Mode Control Register
91
040
98, 102
A16DI
98, 102
A24DI
102
A24P0
98, 102, 106
A24PO
103
A24SLVEN
36, 37
BLEN
106
BLT
106
BLT16
106
DARFEN
106
DMA24
34, 37
DMABEN
106
DMARD
34, 37
FIFOBEN
37
LPBK
106
MBLT
37
NOREL
100, 103
PROT
34, 99, 100
RXATOM
34, 99, 106
TXATOM
99, 100, 103
VINEN
Receive FIFO Address
110 VME 64 SCSI-2 Host Adapter User's Manual
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100, 103
36, 106
36, 106
36, 106
103
36
38
38
Receive FIFO Control
38
Receive FIFO Data
35
VMEbus addressing
VMEbus Base Address Register
VMEbus Interrupt Vector Register
VMEbus mastership timeout
VMEbus Slave Base Address Register
DRAM
See RAM
31, 59, 71
DS1643
52, 53
DSR
52
DTR
52, 59, 72
DUART
Auxiliary Control Register
52
ACR6-ACR4
52
Delta IP1 IRQ
53
Delta IP3 IRQ
Channel A Mode Register
53
Tx RTS Control
General Purpose Timer
Input Port Register
52
IP1
53
IP3
53
IP5
43
Interrupt Request
41
interrupt setup
Output Port Register
53
OPR0
53
OPR1
53
OPR3
53
OPR5
53
OPR6
54
OPR7
E
58
EBOARD
31, 53, 54
EEPROM, serial
42, 58, 59
EPAK
46, 93
address space
42
EPIRQ
20
installation
42
Interrupt Request
41
interrupt setup
Master Bus Error - DRAM Parity
78
Pin assignments
VMEbus Master access
58
zero wait state access
31
EPROM
14
configuration
Example
Initiating DMA transfers
VMEbus Interrupts
99
105
35
102
52
30
47
106