Vmebus Interface; Darf64; Vme 64 Transfers; Transfer Modes - Performance Computer PT-VME151A User Manual

The current state of the individual Interval Timer Request Latches (0, 1, and 2) may be determined by
reading the Interval Timer Interrupt Pending bits in System Status Register 3. SSR3 bits 4, 5, and 6 reflect
the state of ITIP0, ITIP1, and ITIP2, respectively.

VMEbus Interface

The VMEbus interface provides VME64 data transfers as well as a fully functional high performance 32-
bit VMEbus interface as defined by the IEEE 1014 Rev C VMEbus Specification. It is based upon the
Advanced VMEbus Interface Chip Set (AVICS 64) which is comprised of the Advanced VMEbus
System Architecture Control Circuit (ACC) and the VMEbus 64-bit Data Address Register File

(DARF64).

See the DARF64 Data Sheet, the Newbridge Microsystems data book and the AVICS Technical Manual
for more information.
DARF64
The DARF64 is a 64-bit Data/Address Register File which interfaces the VMEbus address and data buses
with the local PT-VME151A bus. It may act as a VMEbus Master or Slave. The local DRAM and EPAK
address spaces of the PT-VME151A are accessible to a VMEbus Master through the DARF64. The
DARF64 is also capable of DMA transfers between local memory (DRAM or EPAK) and the VMEbus.

VME 64 Transfers

VME64 is a newly defined capability of the VMEbus. VMEbus Block Transfer mode (BLT) only uses
the address bus during the first transfer cycle to pass the start address of the transfer. The slave is respon-
sible for latching this address and incrementing it internally as subsequent data arrives. As a result the
address lines on the VMEbus are unused during all but the first transfer. Data is passed every transfer
cycle on the data bus.
The 64 bit Multiplexed Block Transfer (D64MBLT) mode makes a minor change to the first cycle and
takes advantage of the address bus being otherwise unused during a block transfer data phase. A MBLT
cycle is divided into two phases, address and data. During the first transfer cycle address only is passed
and on all subsequent cycles data is passed. The combination of the 32 data lines, 31 address lines, and
the [LWORD*] signal provide a 64 bit path on the VMEbus. A double longword can then be transferred
on each Data Strobe/Data Acknowledge handshake. The address phase can be either A32 or A64. A32
transfers pass the address normally (on the address bus) and the 32 data lines are unused, A64 transfers
pass the high order 32 bits of the 64 bit address on the data lines. During the data phase the 31 address
lines, and the [LWORD*] signal are used to pass the high order 32 bits of the 64 bit data. Specific
Address Modifiers are used to identify A64:D64MBLT and A32:D64MBLT cycles.

Transfer Modes

The DARF64 is capable of two operational modes: "decoupled" and the traditional "atomic". The
decoupled mode takes full advantage of the VMEbus bandwidth by using the receive and transmit
FIFOs, built into the chip, that decouple the local bus from the VMEbus. The FIFOs immediately
accept writes from one bus, release that bus for use, then finish the write to the destination bus. In
atomic mode the DARF64 bypasses the FIFOs, simply buffering the data and address to the desti-
nation bus, forcing any associated wait states back to the source bus.
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Extensible Single Board Computer/Controller User's Manual 33
Performance Computer