System Control Register 2; Enable Epak Access From The Vmebus; Enable Parity Error Checking; Enable Bad Parity - Performance Computer PT-VME151A User Manual

NOTE: If the VMEbus Page Select bit is toggled while caching is enabled a system failure could
result!

System Control Register 2

System Control Register 2 is an 8-bit, read/write register. All bits except ETTI are cleared to zero
(0) by Local Reset. ETTI is set to 1 by Local Reset. This register resides at location 50000000h.

Enable EPAK Access from the VMEbus

The EPAK expansion module can be accessed by a VMEbus master as part of the PT-
VME151A slave image when the EEAV bit is 0, the VMEbus address bit 24 is 1, and the
A32SIZ field of the DARF VMEBAR register is programmed to allow a A32 Slave Image Size
greater than or equal to 32MBytes (Dh). In this case a portion of the PT-VME151A slave image
is replaced by the EPAK's address space. When EPAK accesses from the VMEbus are disabled,
all of the PT-VME151A installed DRAM may be accessed by a VMEbus master. EEAV is
cleared at reset, enable EPAK access. EEAV is register bit 0.

Enable Parity Error Checking

Parity generation and checking is available for the 16M, 32M, and 64M DRAM configurations.
When EPEC is 1, parity checking is enabled for all DRAM reads. Parity errors detected during
68040 or EPAK DRAM reads will return a Bus Error to the respective device. Parity errors
detected during SCSI DMA transfers or DARF64 Local Bus Master cycles will result in an
interrupt request on the ACC's L7IMEM input. The source of the error may be determined by
reading System Status Register 2. See "System Status Register 2" on page 50.
Parity is generated and stored on all DRAM write cycles, regardless of the state of EPEC. If
parity is not available (4M or 8M configurations), parity checking is disabled and EPEC will be
ignored. Reset clears EPEC, disabling parity checking.
NOTE: EPEC should never be set while EBP is set. See "Enable Bad Parity" below.
EPEC is register bit 1.

Enable Bad Parity

For testing purposes it may be desirable to force parity errors. When EBP is 1, the parity bit
written to DRAM with the data is complemented, generating faulty parity. Subsequent read
cycles from the same address will generate parity errors until good parity is written.
NOTE: EBP should never be set while EPEC is set. Otherwise each DRAM write will generate
a parity error.
It should be kept in mind that the 68040 may reorder a sequence of reads and writes in a code
segment. NOPs should be placed in the instruction stream to eliminate the effect. The code
segment to write bad parity should be as follows:
NOP
move.b #$04,$50000000
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;Set EBP and clear EPEC
Extensible Single Board Computer/Controller User's Manual 47
Performance Computer