105
generation
105
receiving
104
VMEbus setup
F
55, 59, 72
FAS216
55, 91
Alternate DMA mode
Configuration Register 3
Alternate DMA mode
46, 56
DMA
42
Interrupt Register
42
Interrupt Request
55
Mode 2
Status Register
42
INT
31
Flash EPROM
14
configuration
73
front panel
40
Abort button
50
hexadecimal switch
74
indicators
38
Reset button
46
User LEDs
H
8
hexadecimal notation
I
92
Initialization requirements
inter-processor communication
see - Location Monitor
71
Interval Timer
41
Interrupt Request
J
14
JEDEC Devices
see ROM, PROM, EPROM, Flash EPROM and SRAM
Jumper Block
9
conventions
67
Default settings
13, 67
K1
15, 67
K10
15, 67
K11
67
K2
15, 67
K3
15, 67
K4
67
K5
17, 67
K6
67
K7
67
K8
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55
91
96
67
K9
12
positions
67
summary
L
38, 45, 46, 47
Local Reset
96
Location Monitor
103
access
60
default address
8
longword data types
M
59
Main Memory
36
burst mode
28
MC68040
8-bit I/O considerations
40, 43, 44
auto-vector interrupts
28
burst mode
Bus Error - DRAM Parity
93
Cache clearing
Cache Control Register
91
Caching
46
caching EPAK space
93
CINV instruction
92
EPAK considerations
93
Exception processing
92
initialization
68
interrupts
non-serialized accesses
92
NOP instruction
Transparent Translation Registers
MC68681, see DUART
9
MC68EC040
59
Memory Map
37
message FIFO
N
Nonvolatile Timekeeping RAM
O
52
OS9
P
30
Parity
31
PROM
14
configuration
52, 60
PTBUG
VME 64 SCSI-2 Host Adapter User's Manual 111
Performance Computer
92
30
92
91
46, 92, 93
31, 59, 71
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