Master Vmebus Accesses - Performance Computer PT-VME151A User Manual

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Section APPENDICES
The A16:D16 region is located at the top of the memory map, in the last 64Kb (FFFF0000h-
FFFFFFFFh). This space can be disabled using the A16DI bit in the DARF64 Mode Control
Register, in which case that address range becomes A32:D32. If the A16 region is enabled and the
CPU accesses that region, the DARF64 will perform the cycle on the VMEbus with address bits 31
through 16 set to one, and will use the address modifier codes indicating short addressing.
Two types of A24 master modes are provided, A24:D16 and A24:D32. By default, the addresses for
both are located at the bottom of the memory map in page 31, A24:D16 in the first 16 Mbytes
(F8000000h-F8FFFFFFh) and A24:D32 in the second 16M bytes (F9000000h-F9FFFFFFh). This
pair of A24 spaces can also be relocated to page 0, in address range 00000000h-00FFFFFFh for
A24:D16 and 01000000h-01FFFFFFh for A24:D32, by using the A24PO bit in the DARF Mode
Control Register. This feature is useful if an A32:D32 device exists at an A24 memory map region.
Within these areas, the DARF64 will set VMEbus address bits 31 through 24 to one, and use the
appropriate address modifier for standard addressing. A24 space can also be disabled by the A24DI
bit, also located in the DARF Mode Control Register, which causes that address range to become
A32:D32.
All of these mapping options affect master VMEbus accesses only; they do not affect accesses to the
card's dual-port memory from the VMEbus. Accesses by the local CPU to its own slave image (if
programmed) are not affected by the VMEbus mapping, nor is the address or data mode affected.
The local memory would be selected within the programmed slave image, and the memory control
logic would provide the required interface signals.

Master VMEbus Accesses

The DARF64 will request the VMEbus for any of the following purposes:
The ACC can be programmed to limit the time that the DARF64 uses the VMEbus, ranging from
immediately off, 2, 4 or 8 microseconds, or unlimited. When the limit is reached, the DARF64 will
complete its current cycle and possibly one more if it has already selected the next one from the
transmit FIFO. Other reasons the ACC can request the DARF64 to give up the VMEbus are pending
VMEbus ownership requests (Release On Request mode), receipt of a Bus Clear from the system
arbiter if Bus Clear recognition is enabled, assertion of L7IMEM to the ACC, or entry into BI-mode.
If the DARF64 is waiting for VMEbus ownership to perform an atomic operation (a write while in
atomic mode, any read or read-modify-write, or an interrupt acknowledge) and some other VMEbus
device begins an atomic operation to the local memory through the DARF64, then the DARF64 will
assert its local bus request signal and request the local CPU to retry its cycle. This will force the CPU
off the bus and allow the incoming cycle to be completed first, resolving the contention. The 68020
and 68030 do not retry read-modify-write cycles so the DARF64 will assert the bus error signal
(BERR).
Entering BI-mode or receiving a local reset will immediately cause the DARF64 to end any VMEbus
cycle in progress. Any cycles remaining in the transmit FIFO will be lost; the CPU cannot unload
them from the FIFO, nor will they be done when the DARF64 leaves BI-mode.
98 Extensible Single Board Computer/Controller User's Manual
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- the transmit FIFO contains write cycles
- the CPU begins a read cycle to the VMEbus
- the DARF64 is in atomic mode and the CPU begins a write cycle to the VMEbus
- the DARF64 is responding to an interrupt request