Iack Daisy Chain Driver; Bus Timer; I/O Utilities; System Control Registers - Performance Computer PT-VME151A User Manual

I/O UTILITIES

System Control Registers

The System Control Registers provide the PT-VME151A with miscellaneous control functions not
provided in other registers. They are all 8-bit, read/write registers.
These registers can be read back. This allows the use of AND or OR instructions to clear and set indi-
vidual bits.
!
CAUTION: These registers should only be referenced using byte operations! Reading any of them as a
word or longword will be translated into multiple byte reads by the sizing logic, with the same data byte
being repeated on each reference. Writing them as a word or longword can cause problems because the
bus sizing forces multiple byte writes to occur. This will leave only the last (most significant) byte in the
selected register. The other bytes will have previously been pumped through the register and if they are
not identical to the MSB the respective bits of the control register will toggle.

System Control Register 1

System Control Register 1 is an 8-bit, read/write register. All bits are cleared to zero (0) by Local
Reset. It resides at location 0D000000h.
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The arbitration mode is determined by the ARB1 and ARB0 bits in the ACC VMEbus
Arbiter Register. The possible modes are: Full Round Robin. Bus Request Level 3 has
priority over levels 2, 1, and 0 which are handled in Round Robin mode. Bus Request
Levels 3 and 2 have priority over levels 1 and 0 which are handled in Round Robin mode.
And, full Priority mode.
Arbitration time-out is enabled by the ATEN bit in the ACC VMEbus Arbiter Register. The
Bus Grant issued by the arbiter will be withdrawn after 16 us, if no card asserts BBSY* to
take ownership of the VMEbus. The arbiter then waits 16 us to allow the deasserted grant
to fully propagate through the daisy chain, then rearbitrates the bus.

IACK Daisy Chain Driver

The IACK Daisy Chain Driver (DCD) performs the standard VMEbus System Controller
IACK DCD function, as well as providing the VMEbus Interrupt Generator logic.

Bus Timer

The ACC as System Controller provides VMEbus Data Transfer Time-out functionality.
VMEbus data transfers are terminated with the error signal BERR*, if a slave does not
respond within a programmed time. The time-out period may be 16, 32, or 64 us, or
"never". The default value after reset is 64 us. The VXL1 and VXL0 control bits in the ACC
VMEbus Arbiter Register determine the time-out period.
Extensible Single Board Computer/Controller User's Manual 45
Performance Computer