Performance Computer PT-VME151A User Manual page 78

System Control Register 2
Bit Name
0 EEAV
1 EPEC
2 EBP
4-3 RITI
5 EITI
6 ETTI
7
1
DRAM MUST be initialized before parity checking is enabled.
2
DO NOT enable if EBP = 1.
3
DO NOT enable if EPEC = 1.
4
RITI always read as 0.
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Address 50000000h
Byte Read/Write Only
All bits cleared to zero by reset, except ETTI
7 6 5 4 3
Function
Enable EPAK Access from VMEbus
1 Enable EPAK Access from VMEbus when A24 = 1
0 Disable EPAK Access from VMEbus
1,2
Enable Parity Error Checking
1 Check for parity errors
0 Do not check for parity errors
3
Enable Bad Parity
1 Write bad parity
0 Write normal parity
4
Reset Interval Timer Interrupt pending latch
3 Reset Interval Timer 2 Interrupt Pending Latch
2 Reset Interval Timer 1 Interrupt Pending Latch
1 Reset Interval Timer 0 Interrupt Pending Latch
0 No action
Enable Interval Timer Interrupts
1 Enable interrupts
0 Disable interrupts
Enable Tick Timer Interrupts
1 Enable interrupts
0 Disable interrupts
Reserved, mask to zero when read
Extensible Single Board Computer/Controller User's Manual 63
2 1 0
EEAV
EPEC
EBP
RITI
EITI
ETTI
Reserved
Performance Computer