Slave Vmebus Accesses - Performance Computer PT-VME151A User Manual

Performance Computer
The transmit and receive channels of the DARF64 can each be programmed to operate in atomic or
decoupled mode by using the RXATOM and TXATOM bits in the DARF Mode Control Register.
Read cycles and interrupt acknowledge cycles are always atomic. In atomic mode accesses, the CPU
transfer is not enqueued by the transmit FIFO; the CPU becomes directly linked to the VMEbus once
ownership is obtained. The CPU will then execute wait states until an acknowledge or bus error is
generated by the VMEbus slave.
CPU write cycles to the VMEbus, with the DARF64 transmit channel in decoupled mode, complete
with no wait states. The transmit FIFO will enqueue (both FIFOs are 15 stages deep) the address,
data and control signals needed to perform the cycle on the VMEbus. Once the DARF64 has
obtained the VMEbus, it will begin the cycles, operating with close to minimum VMEbus specified
timing to start and end each cycle. A pending atomic cycle from the local CPU will wait until all
write cycles loaded in the FIFO are completed first, so that data integrity is maintained - read cycles
cannot skip ahead of uncompleted write cycles.
A VME bus error received by the DARF64 will cause it to stop performing VMEbus cycles, set the
VBERR bit in DARF Control and Status Register, and generate an interrupt to the CPU. The
DARF64 will not allow further VMEbus master cycles until the VBERR bit is cleared. If the
DARF64 is in decoupled mode, the remaining cycles in the transmit FIFO will begin being sent
again once VBERR is cleared. The failed cycle is not re-run by the DARF64 since it no longer is in
the FIFO. Three registers in the DARF64 (TDATA, TADDR, TCTL) can be used by the CPU to read
the output stage of the FIFO to determine the address, data, and control codes involved in the failed
write cycle.
If the FIFO is full when the CPU writes to the VMEbus in decoupled mode, the DARF64 will not
respond and the CPU will attempt to wait until there is room. If the local bus timeout has been
enabled in the ACC, and the CPU waits for longer than 512 microseconds for access to the FIFO,
then the CPU will receive a local bus error and set the LBERR bit in the DARF Control and Status
Register and the local timeout bit (LTO) in ACC Status Register 0.

Slave VMEbus Accesses

The AVICs allows some, all, or none of the local memory to be accessible as a VMEbus slave
through the programming of a "slave image". This image can vary in its VMEbus base address, size,
and access protection range. Separate images can be set up in A24 and A32 address spaces. The local
CPU can also access its own slave image at their programmed addresses, within the size configured;
however, the DARF64 only acts as an address decoder and does not implement access protection,
use the VMEbus or its FIFOs, unless the DARF64 is in loopback mode.
The DARF64 does not provide a slave image on the VMEbus until its base address and image size
have been programmed in the DARF VMEbus Base Address Register. The BARDY bit in the DARF
Control and Status Register indicates whether the slave image has been programmed since a reset
condition occurred. The VINEN bit in the DARF Mode Control Register is used to enable or disable
the slave images on the VMEbus.
The A24 and A32 slave images are defined by the VMEbus Base Address Register. The A24 image
base can be programmed to any half megabyte boundary or multiple of its programmed size, which-
ever is larger, within the 16Mb A24 addressing space. The size of this image can be set to 512Kb,
1, 2, or 4Mb. The A32 image base can be programmed to any 128Mb boundary and to any size from
4Kb to 128Mb in binary increments (i.e. 4k, 8k, 16k, etc.) The location monitor appears at the last
longword of each programmed slave image.
Although the slave image bases and sizes can be programmed to many values, only certain combi-
nations are valid. The restriction described below ensures that when the local memory is addressed
Extensible Single Board Computer/Controller User's Manual 99
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