Setting Up The Master Bus Memory Map; Example; Setting Up A24/A32 Slave Images On The Bus - Performance Computer PT-VME151A User Manual

7
Section APPENDICES

Setting Up the Master Bus Memory Map

When the host accesses the VMEbus, the address used by the CPU determines the address and data
modes the DARF will use to perform the cycle. All outgoing VMEbus accesses are affected by a
programmed memory map. See "DARF Memory Map" on page 97. Memory Map Pages 1-30 are dedi-
cated to A32 space, while pages 0 and 31 can be customized by the following steps:
!
CAUTION: For PTI products, one must set bit 31 of the address to specify that it is a VME address. The
PAGE bit in the Control Register is then used as bit 31 of the VME address before being used by the
DARF. From this point forward, all address references will be in respect to what the DARF sees.
Step 1
Step 2
Step 3
Step 4

Example:

To set up a master memory map with A16 disabled and A24 space located at page 0, perform the
following steps:
Step 1
Step 2
Step 3
Step 4

Setting Up A24/A32 Slave Images on the Bus

In order for other boards in a VMEbus system to access the host's DRAM, the following steps must be
taken to present a slave image onto the bus:
Step 1
102 Extensible Single Board Computer/Controller User's Manual
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Make sure the system is not in BI-mode (refer to steps 6-9 of Setting Up A24/A32 Slave
Images) if VMEbus accesses are desired.
Clear the A16DI bit in the DARF Mode Control Register, if the A16 region is desired; set
this bit to disable A16 space, in which case that address range becomes A32. When A16
space is enabled, the local CPU can access the region by using the address range
FFFF0000h-FFFFFFFF. The low four bytes constitute the actual VME address of the 16-
bit device, while the upper four bytes tells the DARF to generate a D16 address modifier.
Clear the DARF Mode Control Register, A24DI bit to enable A24 space; set this bit to
disable the A24 space programmed in the memory map which causes that space to become
A32.
Set the DARF Mode Control Register, A24PO bit to assign page 31 as A24 space; clear it
to locate A24 space in page 0. Addresses 00000000h-00FFFFFFh (if in page 0) and
F8000000h-F8FFFFFFh (if in page 31) are used to perform an A24:D16 cycle. Addresses
01000000h- 01FFFFFFh (if in page 0) and F9000000h-F9FFFFFFh (if in page 31) are used
to perform an A24:D32 cycle.
Exit BI-mode if VMEbus accesses are desired. Follow steps 7-9 of the section "Setting Up
A24/A32 Slave Images on the Bus" in this appendix.
Set DARF Mode Control Register A16DI bit to disable the A16 space.
Clear DARF Mode Control Register A24DI bit to enable the A24 space.
Set DARF Mode Control Register A24P0 bit to locate the A24 space at 00xxxxxxh of VME
space.
Program DARF VMEbus Slave Base Address Register with appropriate A24 and/or A32
image size and base address value according to the register description.