Watchdog Timer; Watchdog Timer Clock So�Rce; Watchdog Timer Control Register - Holtek HT66F20 Manual

Watchdog Timer

The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal clock, f
one of two sources selected by configuration option: f
from either the LXT or LIRC oscillators, again chosen via a configuration option. The Watchdog
Timer source clock is then subdivided by a ratio of 2
being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an
approximate period of 32kHz at a supply voltage of 5V.
However, it should be noted that this specified internal clock period can vary with V
and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. The other
Watchdog Timer clock source option is the f
originate from its own internal LIRC oscillator, the LXT oscillator or f
of 2 to 2 , using the WS2~WS0 bits in the WDTC register to obtain the required Watchdog Timer
8 15
time-out period.

Watchdog Timer Control Register

A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. This register together with several configuration options control the overall operation of
the Watchdog Timer.
WDTC Register
Bit 7
Name FSYSON
R/W R/W
POR 0
Bit 7 FSYSON: f
0: Disable
1: Enable
Bit 6~4 WS2, WS1, WS0: WDT time-out period selection
000: 256/f
001: 512/f
010: 1024/f
011: 2048/f
100: 4096/f
101: 8192/f
110: 16384/f
111: 32768/f
These three bits determine the division ratio of the Watchdog Timer source clock,
which in turn determines the timeout period.
Bit 3~0 WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT Software Control
1010: Disable
Other: Enable
Rev. 2.50
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
to 2
8
/4 clock. The Watchdog Timer clock source can
SYS
6 5 4 3
WS2 WS� WS0 WDTEN3
R/W R/W R/W R/W
� � � �
Control in IDLE Mode
SYS
S
S
S
S
S
S
S
S
68
, which is in turn supplied by
S
or f /4. The f clock can be sourced
SUB SYS SUB
to give longer timeouts, the actual value
15
DD
/4. It is divided by a value
SYS
2 1
WDTEN2 WDTEN�
R/W R/W
0 �
��ne 22� 20��
, temperature
0
WDTEN0
R/W
0