Holtek HT66F20 Manual page 243

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
Bit 2 RXIF: Receive RXR data register status
0: RXR data register is empty
1: RXR data register has available data
The RXIF flag is the receive data register status flag. When this read only flag is 0,
it indicates that the RXR read data register is empty. When the flag is 1, it indicates
that the RXR read data register contains new data. When the contents of the shift
register are transferred to the RXR register, an interrupt is generated if RIE=1 in the
UCR2 register. If one or more errors are detected in the received word, the appropriate
receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The
RXIF flag is cleared when the USR register is read with RXIF set, followed by a read
from the RXR register, and if the RXR register has no data available.
Bit 1 TIDLE: Transmission idle
0: Data transmission is in progress (data being transmitted)
1: No data transmission is in progress (transmitter is idle)
The TIDLE flag is known as the transmission complete flag. When this read only flag
is 0, it indicates that a transmission is in progress. This flag will be set to 1 when the
TXIF flag is 1 and when there is no transmit data or break character being transmitted.
When TIDLE is equal to 1, the TX pin becomes idle with the pin state in logic high
condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and
then writing to the TXR register. The flag is not generated when a data character or a
break is queued and ready to be sent.
Bit 0 TXIF: Transmit TXR data register status
0: character is not transferred to the transmit shift register
1: character has transferred to the transmit shift register (TXR data register is empty)
The TXIF flag is the transmit data register empty flag. When this read only flag is 0, it
indicates that the character is not transferred to the transmitter shift register. When the
flag is 1, it indicates that the transmitter shift register has received a character from the
TXR data register. The TXIF flag is cleared by reading the UART status register (USR)
with TXIF set and then writing to the TXR data register. Note that when the TXEN bit
is set, the TXIF flag bit will also be set since the transmit data register is not yet full.
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