A/D Operation - Holtek HT66F20 Manual

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM

A/D Operation

The START bit in the ADCR0 register is used to start and reset the A/D converter. When the
microcontroller sets this bit from low to high and then low again, an analog to digital conversion
cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB
bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It is the
START bit that is used to control the overall start operation of the internal analog to digital converter.
The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion
process is complete. This bit will be automatically set to 0 by the microcontroller after a conversion
cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt
control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be
generated. This A/D internal interrupt signal will direct the program flow to the associated A/D
internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller
can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an
alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock f
to be either f or a subdivided version of f
SYS
ADCK2~ADCK0 bits in the ADCR1 register.
Although the A/D clock source is determined by the system clock f
there are some limitations on the maximum A/D clock source speed that can be selected. As the
minimum value of permissible A/D clock period, t
frequencies equal to or greater than 4MHz. For example, if the system clock operates at a frequency
of 4MHz, the ADCK2~ADCK0 bits should not be set to 000. Doing so will give A/D clock periods
that are less than the minimum A/D clock period which may result in inaccurate A/D conversion
values. Refer to the following table for examples, where values marked with an asterisk * show
where, depending upon the device, special care must be taken, as the values may be less than the
specified minimum A/D Clock Period.
ADCK2,
ADCK1,
f
SYS
ADCK0
=000
(f )
SYS
�MHz 1μs
2MHz 500ns
4MHz 250ns*
8MHz �25ns*
�2MHz 83ns*
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When
the ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay,
as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even
if no pins are selected for use as A/D inputs by clearing the ACE11~ACE0 bits in the ACERH
and ACERL registers, if the ADOFF bit is zero then some power will still be consumed. In power
conscious applications it is therefore recommended that the ADOFF is set high to reduce power
consumption when the A/D converter function is not being used.
The reference voltage supply to the A/D Converter can be supplied from either the positive power
supply pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection
is made using the VREFS bit. As the VREF pin is pin-shared with other functions, when the VREFS
bit is set high, the VREF pin function will be selected and the other pin functions will be disabled
automatically.
Rev. 2.50
. The division ratio value is determined by the
SYS
ADCK
A/D Clock Period (t
ADCK2, ADCK2, ADCK2,
ADCK1, ADCK1, ADCK1,
ADCK0 ADCK0 ADCK0
=001 =010 =011
(f /2) (f /4) (f /8)
SYS SYS SYS
2μs 4μs 8μs
1μs 2μs 4μs
500ns 1μs 2μs
250ns* 500ns 1μs
�6�ns* 333ns* 66�ns
A/D Clock Period Examples
��5
, can be chosen
SYS
, and by bits ADCK2~ADCK0,
SYS
, is 0.5μs, care must be taken for system clock
)
ADCK
ADCK2, ADCK2, ADCK2,
ADCK1, ADCK1, ADCK1,
ADCK0 ADCK0 ADCK0
=100 =101 =110
(f /16) (f /32) (f /64)
SYS SYS SYS
16μs 32μs 64μs
8μs 16μs 32μs
4μs 8μs 16μs
2μs 4μs 8μs
1.33μs 2.67μs 5.33μs
��ne 22� 20��
ADCK2,
ADCK1,
ADCK0
=111
Undefined
Undefined
Undefined
Undefined
Undefined