Holtek HT66F20 Manual page 14

1 2 8
P A 0 / C 0 X / T P 0 _ 0 / A N 0
V S S & A V S S 2 2 7
P B 4 / X T 2 3 2 6
P B 3 / X T 1 4 2 5
P B 2 / O S C 2 5 2 4
P B 1 / O S C 1 6 2 3
V D D 7 2 2
P B 0 / R E S 8 2 1
P C 1 / T P 1 B _ 1 / S C O M 1 9 2 0
P C 0 / T P 1 B _ 0 / S C O M 0 1 0 1 9
P C 7 / [ T P 1 A ] / S C O M 3 1 1 1 8
P C 6 / [ T P 0 _ 0 ] / S C O M 2 1 2 1 7
P D 3 / [ T C K 1 ] / T P 3 _ 0 / [ S D O ] 1 3 1 6
1 4 1 5
P D 2 / [ T C K 0 ] / [ S D I / S D A ]
H T 6 6 F 5 0
2 8 S K D I P - A / S O P - A / S S O P - A
P A 0 / C 0 X / T P 0 _ 0 / A N 0
1 4 8
P F 1 / [ C 1 X ] 4 7
2
P F 0 / [ C 0 X ]
3 4 6
P E 7 / [ I N T 1 ] 4 5
4
P E 6 / [ I N T 0 ]
5 4 4
V S S & A V S S 4 3
6
P B 4 / X T 2
7 4 2
P B 3 / X T 1
8 4 1
P B 2 / O S C 2
9 4 0
P B 1 / O S C 1
1 0 3 9
V D D & A V D D 3 8
1 1
P B 0 / R E S
1 2 3 7
P E 5 / [ T P 3 _ 0 ] 3 6
1 3
P E 4 / [ T P 1 B _ 2 ]
1 4 3 5
P C 1 / T P 1 B _ 1 / S C O M 1 3 4
1 5
P C 0 / T P 1 B _ 0 / S C O M 0
1 6 3 3
N C 3 2
1 7
P C 7 / [ T P 1 A ] / S C O M 3
1 8 3 1
P C 6 / [ T P 0 _ 0 ] / S C O M 2 3 0
1 9
P E 3 / [ T P 3 _ 1 ]
2 0 2 9
P E 2
2 1 2 8
P E 1
2 2 2 7
P E 0
2 3 2 6
P D 5 / [ T P 0 _ 1 ] 2 5
2 4
H T 6 6 F 5 0
4 8 S S O P - A
Note: 1. Bracketed pin names indicate non-default pinout remapping locations.
2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the
"/" sign can be used for higher priority.
3. VDD&AVDD means the VDD and AVDD are the double bonding.
Rev. 2.50
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
P A 1 / T P 1 A / A N 1
P A 2 / T C K 0 / C 0 + / A N 2
P A 3 / I N T 0 / C 0 - / A N 3
P A 4 / I N T 1 / T C K 1 / A N 4
P A 5 / C 1 X / S D O / A N 5
P A 6 / S D I / S D A / A N 6
P A 7 / S C K / S C L / A N 7
P B 5 / S C S / V R E F
P A 7 / S C K / S C L / A N 7
P B 5 / S C S / V R E F
P A 6 / S D I / S D A / A N 6
P C 2 / T C K 2 / P C K / C 1 +
P A 5 / C 1 X / S D O / A N 5
P C 3 / P I N T / T P 2 _ 0 / C 1 -
P A 4 / I N T 1 / T C K 1 / A N 4
P A 3 / I N T 0 / C 0 - / A N 3
P C 4 / [ I N T 0 ] / [ P I N T ] / T C K 3 / T P 2 _ 1
P A 2 / T C K 0 / C 0 + / A N 2
P C 5 / [ I N T 1 ] / T P 0 _ 1 / T P 1 B _ 2 / [ P C K ]
P A 1 / T P 1 A / A N 1
P D 0 / [ T C K 2 ] / T P 3 _ 1 / [ S C S ]
P A 0 / C 0 X / T P 0 _ 0 / A N 0
P D 1 / [ T P 2 _ 0 ] / [ S D O ] / [ S C K / S C L ]
P A 1 / T P 1 A / A N 1
P A 2 / T C K 0 / C 0 + / A N 2
P A 3 / I N T 0 / C 0 - / A N 3
P A 4 / I N T 1 / T C K 1 / A N 4
P A 5 / C 1 X / S D O / A N 5
P A 6 / S D I / S D A / A N 6
P A 7 / S C K / S C L / A N 7
P B 5 / S C S / V R E F
P B 6 / [ S D O ]
P B 7 / [ S D I / S D A ]
P D 6 / [ S C K / S C L ]
P D 7 / [ S C S ]
P B 5 / S C S / V R E F
P C 4 / [ I N T 0 ] / [ P I N T ] / T P 2 _ 1
P A 7 / S C K / S C L / A N 7
P A 6 / S D I / S D A / A N 6
N C
P A 5 / C 1 X / S D O / A N 5
N C
P A 4 / I N T 1 / T C K 1 / A N 4
N C
P A 3 / I N T 0 / C 0 - / A N 3
P A 2 / T C K 0 / C 0 + / A N 2
P C 2 / T C K 2 / P C K / C 1 +
P A 1 / T P 1 A / A N 1
P C 3 / P I N T / T P 2 _ 0 / C 1 -
P A 0 / C 0 X / T P 0 _ 0 / A N 0
P C 5 / [ I N T 1 ] / T P 0 _ 1 / T P 1 B _ 2 / [ P C K ]
P F 1 / [ C 1 X ]
P D 0 / [ T C K 2 ] / [ S C S ] P F 0 / [ C 0 X ]
P D 1 / [ T P 2 _ 0 ] / [ S D O ] / [ S C K / S C L ]
P D 2 / [ T C K 0 ] / [ S D I / S D A ]
P D 3 / [ T C K 1 ] / [ S D O ]
P D 4 / [ T P 2 _ 1 ]
P B 5 / S C S / V R E F
P A 7 / S C K / S C L / A N 7
P A 6 / S D I / S D A / A N 6
P A 5 / C 1 X / S D O / A N 5
P A 4 / I N T 1 / T C K 1 / A N 4
P A 3 / I N T 0 / C 0 - / A N 3
P A 2 / T C K 0 / C 0 + / A N 2
P A 1 / T P 1 A / A N 1
P A 0 / C 0 X / T P 0 _ 0 / A N 0
P F 1 / [ C 1 X ]
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A/D Flash MCU with EEPROM
4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1
1 3 0 P D 2 / [ T C K 0 ] / [ S D I / S D A ]
2
2 9 P D 3 / [ T C K 1 ] / T P 3 _ 0 / [ S D O ]
2 8 P D 4 / [ T P 2 _ 1 ]
3
4 2 7 P D 5 / [ T P 0 _ 1 ]
5 H T 6 6 F 5 0 2 6 P C 6 / [ T P 0 _ 0 ] / S C O M 2
6 4 0 Q F N - A 2 5 P C 7 / [ T P 1 A ] / S C O M 3
7
2 4 P C 0 / T P 1 B _ 0 / S C O M 0
8 2 3 P C 1 / T P 1 B _ 1 / S C O M 1
P E 4 / [ T P 1 B _ 2 ]
9 2 2
1 0 P E 5 / [ T P 3 _ 0 ]
P F 1 / [ C 1 X ] 2 1
1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
P D 3 / [ T C K 1 ] / T P 3 _ 0 / [ S D O ]
1 3 3
2 3 2 P D 4 / [ T P 2 _ 1 ]
3 P D 5 / [ T P 0 _ 1 ]
3 1
4 P E 0
3 0
5 P E 1
2 9
H T 6 6 F 5 0
6 P E 2
2 8
4 4 L Q F P - A
7 P E 3 / [ T P 3 _ 1 ]
2 7
8 P C 6 / [ T P 0 _ 0 ] / S C O M 2
2 6
9 P C 7 / [ T P 1 A ] / S C O M 3
2 5
P C 0 / T P 1 B _ 0 / S C O M 0
1 0
2 4
P C 1 / T P 1 B _ 1 / S C O M 1
1 1 2 3
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
4 2
4 8 4 7 4 6 4 5 4 4 4 3 4 1 4 0 3 9 3 8 3 7
N C 1 3 6 P D 3 / [ T C K 1 ] / T P 3 _ 0 / [ S D O ]
2 3 5 P D 4 / [ T P 2 _ 1 ]
3 3 4 P D 5 / [ T P 0 _ 1 ]
P E 0
4 3 3
P E 1
5 3 2
P E 2
6 H T 6 6 F 5 0 3 1
7 4 8 Q F N - A 3 0 P E 3 / [ T P 3 _ 1 ]
8 2 9 P C 6 / [ T P 0 _ 0 ] / S C O M 2
P C 7 / [ T P 1 A ] / S C O M 3
9 2 8
N C
1 0 2 7
N C P C 0 / T P 1 B _ 0 / S C O M 0
1 1 2 6
P C 1 / T P 1 B _ 1 / S C O M 1
1 2 2 5
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
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