Co�nter overflow
Co�nter Val�e
CCRP=0
0x3FF
CCRP
CCRA
TnON
TnPAU
TnAPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TPnA O/P
Pin
O�tp�t pin set to
O�tp�t Toggle with
initial Level Low
if TnAOC=0
Here TnAIO [�:0] = ��
Toggle O�tp�t select
ETM CCRA Compare Match Output Mode – TnCCLR=0
Note: 1. With TnCCLR=0, a Comparator P match will clear the counter
2. The TPnA output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
Rev. 2.50
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
CCRP > 0
Co�nter cleared by CCRP val�e
CCRP > 0
O�tp�t not affected by TnAF
flag. Remains High �ntil reset
by TnON bit
TnAF flag
Note TnAIO [�:0] = �0
Active High O�tp�t select
�54
A/D Flash MCU with EEPROM
TnCCLR = 0; TnAM [�:0] = 00
Co�nter
Res�me
Restart
Pa�se
Stop
O�tp�t Pin
Reset to Initial val�e
O�tp�t controlled by
other pin-shared f�nction
Time
O�tp�t Inverts
when TnAPOL is high
��ne 22� 20��
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