Holtek HT66F20 Manual page 196

Bit 0 RXAK: I
0: Slave receive acknowledge flag
1: Slave do not receive acknowledge flag
The RXAK flag is the receiver acknowledge flag. When the RXAK flag is 0, it means
that a acknowledge signal has been received at the 9th clock, after 8 bits of data have
been transmitted. When the slave device in the transmit mode, the slave device checks
the RXAK flag to determine if the master receiver wishes to receive the next byte. The
slave transmitter will therefore continue sending out data until the RXAK flag is 1.
When this occurs, the slave transmitter will release the SDA line to allow the master to
send a STOP signal to release the I
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I
be transmitted must be placed in the SIMD register. After the data is received from the I
device can read it from the SIMD register. Any transmission or reception of data from the I
must be made via the SIMD register.
• SIMD Register
Bit 7
Name D�
R/W R/W
POR ×
• SIMA Register
Bit 7
Name IICA6
R/W R/W
POR ×
IICA6~IICA0: I
Bit 7~1
IICA6~IICA0 is the I
The SIMA register is also used by the SPI interface but has the name SIMC2. The
SIMA register is the location where the 7-bit slave address of the slave device is
stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not
defined.
When a master device, which is connected to the I
matches the slave address in the SIMA register, the slave device will be selected. Note
that the SIMA register is the same register address as SIMC2 which is used by the SPI
interface.
Bit 0 Undefined bit
This bit can be read or written by user software program.
Rev. 2.50
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
C Bus Receive acknowledge flag
2
C Bus.
2
C functions. Before the device writes data to the I
2
6 5 4
D6 D5 D4
R/W R/W R/W
× × ×
6 5 4
IICA5 IICA4 IICA3
R/W R/W R/W
× × ×
C slave address
2
C slave address bit 6~bit 0.
2
�96
C bus, the actual data to
2
2
3 2 1
D3 D2 D�
R/W R/W R/W
× × ×
"×" �nknown
3 2 1
IICA2 IICA� IICA0
R/W R/W R/W
× × ×
"×" �nknown
C bus, sends out an address, which
2
��ne 22� 20��
C bus, the
C bus
2
0
D0
R/W
×
0
—
—
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