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GPIO Registers
5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL)
The PIPOL determines the GPIO pin signal polarity that generates an interrupt.
The video port pin interrupt polarity register (PIPOL) is shown in
31
23
22
Reserved
PIPOL22
R-0
R/W-0
15
14
PIPOL15
PIPOL14
R/W-0
R/W-0
7
6
PIPOL7
PIPOL6
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-11. Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions
(1)
Bit
field
symval
31-23 Reserved
-
22
PIPOL22
OF(value)
DEFAULT
VCTL3ACTHI
VCTL3ACTLO
21
PIPOL21
OF(value)
DEFAULT
VCTL2ACTHI
VCTL2ACTLO
20
PIPOL20
OF(value)
DEFAULT
VCTL1ACTHI
VCTL1ACTLO
19-2
PIPOL[19-2]
OF(value)
DEFAULT
VDATAnACTHI
VDATAnACTLO
(1)
For CSL implementation, use the notation VP_PIPOL_PIPOLn_symval.
164
General-Purpose I/O Operation
Figure 5-10. Video Port Pin Interrupt Polarity Register (PIPOL)
21
20
PIPOL21
PIPOL20
R/W-0
R/W-0
13
12
PIPOL13
PIPOL12
R/W-0
R/W-0
5
4
PIPOL5
PIPOL4
R/W-0
R/W-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
PIPOL22 bit determines the VCTL3 pin signal polarity that generates an interrupt.
0
Interrupt is caused by a low-to-high transition on the VCTL3 pin.
1
Interrupt is caused by a high-to-low transition on the VCTL3 pin.
PIPOL21 bit determines the VCTL2 pin signal polarity that generates an interrupt.
0
Interrupt is caused by a low-to-high transition on the VCTL2 pin.
1
Interrupt is caused by a high-to-low transition on the VCTL2 pin.
PIPOL20 bit determines the VCTL1 pin signal polarity that generates an interrupt.
0
Interrupt is caused by a low-to-high transition on the VCTL1 pin.
1
Interrupt is caused by a high-to-low transition on the VCTL1 pin.
PIPOL[19-2] bit determines the corresponding VDATA[n] pin signal polarity that
generates an interrupt.
0
Interrupt is caused by a low-to-high transition on the VDATA[n] pin.
1
Interrupt is caused by a high-to-low transition on the VDATA[n] pin.
Figure 5-10
Reserved
R-0
19
18
PIPOL19
PIPOL18
R/W-0
R/W-0
11
10
Reserved
Reserved
R-0
R-0
3
2
PIPOL3
PIPOL2
R/W-0
R/W-0
www.ti.com
and described in
Table
5-11.
24
17
16
PIPOL17
PIPOL16
R/W-0
R/W-0
9
8
PIPOL9
PIPOL8
R/W-0
R/W-0
1
0
Reserved
Reserved
R-0
R-0
SPRUEM1 – May 2007
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