Horizontal Ancillary (Hanc) Data Capture; Vertical Ancillary (Vanc) Data Capture; Raw Data Capture Mode; Raw Data Capture Notification - Texas Instruments TMS320DM648 User Manual

Video port/vcxo interpolated control (vic) port
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3.6.1 Horizontal Ancillary (HANC) Data Capture

No special provisions are made for the capture of HANC data. HANC data may be captured using the
normal video capture mechanism by programming VCXSTRT to occur before the SAV (when HCOUNT is
reset by the EAV code) or by programming VCXSTOP to occur past the EAV code (when HCOUNT is
reset by the SAV code). Note that the EAV code and any subsequent HANC data will still be YCbCr
separated. Software must parse the Y, Cb, and Cr memory buffers to determine any HANC data presence
and to reconstruct the HANC data. The VCTHRLD value and EDMA size must be programmed to
comprehend the additional samples. You must disable scaling and chroma re-sampling when including the
capture of HANC data to prevent data corruption.

3.6.2 Vertical Ancillary (VANC) Data Capture

VANC (or VBI) data is commonly used for such features as teletext and closed-captioning. No special
provisions are made for the capture of VBI data. VBI data may be captured using the normal capture
mechanism by programming VCYSTART to occur before the first line of active video on the first line of
desired VBI data. (VCOUNT must be reset by an EAV with V = 1). Note that the VBI data will be YCbCr
separated. Software must parse the Y, Cb, and Cr memory buffers to determine any VBI data presence
and to reconstruct the VBI data. You must disable scaling and chroma re-sampling when the capture of
VBI data is desired or the data will be corrupted by the filters.
3.7

Raw Data Capture Mode

In the raw data capture mode, the data is sampled by the interface only when the CAPEN signal is active.
Data is captured at the rate of the sender's clock, without any interpretation or start/stop of capture based
on the data values.
To ensure initial capture synchronization to the beginning of a frame, an optional setup synchronization
enable (SSE) bit is provided in VCxSTRT1. If the SSE bit is set, then when the VCEN bit is set to 1, the
video port will not start capturing data until after detecting two vertical blanking intervals. If the SSE bit is
cleared to 0, capture begins immediately when the VCEN bit is set.
The incoming digital video capture data is stored in the FIFO, which is 2560-bytes (in dual-channel
operation) or 5120-bytes deep (in single-channel operation). The memory-mapped location YSRCx is
associated with the Y buffer. The YSRCx location is a read-only register and is used to access video data
samples stored in the buffer.
The captured data set size(image size) is set by VCxSTOPn. The VCXSTOP and VCYSTOP bits set the
24-bits of data set size(VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits). Capture
is complete and the appropriate F1C, F2C, or FRMC bit is set when the captured data size reaches the
combined VCYSTOP and VCXSTOP value. The CAPEN signal must go inactive for a minimum of two
VPCLK cycles after the pixel count has expired. Keeping the CAPEN signal active after the pixel count
expires may cause a loss of pixels; therefore, it is not recommended to permanently enable the CAPEN
signal during raw data capture mode.
The video port generates a YEVT after the specified number of new samples has been captured in the
buffer. The number of samples required to generate YEVTx is programmable and is set in the VCTHRLDn
bits of VCxTHRLD. On every YEVT, the EDMA should move data from the buffer to the DSP memory.
When moving data from the buffer to the DSP memory, the EDMA should use the YSRCx location as a
source address.

3.7.1 Raw Data Capture Notification

Raw data mode captures a single data packet of information using only CAPEN for control. Field
information is available only for channel A operation using the FID input on VCTL3. If the RDFE bit in
VCACTL is set, then the video port samples the FID input at the start of each data block (when DCOUNT
= 0 and CAPENA is active) to determine the current field. In this case, the CON, FRAME, CF1, and CF2
bits in VCxCTL are used in a manner identical to BT.656 mode (see
SPRUEM1 – May 2007
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Raw Data Capture Mode

Section
3.4.1).
Video Capture Port
61

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