Page 1 TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide Literature Number: SPRU592E April 2005...
Page 2 Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com. TMS320VC5501 Fixed-Point Digital Signal Processor Data Manual (literature number SPRS206) describes the features of the TMS320VC5501 fixed-point DSP and provides signal descriptions, pinouts, electrical specifications, and timings for the device.
Page 3 Related Documentation From Texas Instruments TMS320VC5502 Fixed-Point Digital Signal Processor Data Manual (literature number SPRS166) describes the features of the TMS320VC5502 fixed-point DSP and provides signal descriptions, pinouts, electrical specifications, and timings for the device. TMS320VC5503 Fixed-Point Digital Signal Processor Data Manual (litera-...
Page 4 Related Documentation From Texas Instruments Related Documentation From Texas Instruments / Trademarks TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature number SPRU375) describes the TMS320C55x DSP algebraic instructions individually. Also includes a summary of the instruction set, a list of the instruction opcodes, and a cross-reference to the mnemonic instruction set.
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Page 6: Table Of Contents
Contents Contents Introduction to the McBSP ............Introduction .
Page 7 Contents 3.2.3 Choosing a Frequency for the Output Clock (CLKG) ..... 3.2.4 Keeping CLKG Synchronized to an External Input Clock .
Page 8 Contents 5.7.1 Disabling/Enabling Versus Masking/Unmasking ......5-12 5.7.2 Activity on McBSP Pins for Different Values of XMCM .
Page 9 Contents 7.17.1 About Frame Sync Pulses, Clock Signals, and Their Polarities ... 7-26 7.18 Setting the SRG Frame-Sync Period and Pulse Width ......7-29 7.18.1 About the Frame-Sync Period and the Frame-Sync Pulse Width .
Page 10 ........... 10-3 10.3 McBSP Power Management on the TMS320VC5501 and TMS320VC5502 Devices .
Page 11 Contents 12.4 Receive Control Registers (RCR1 and RCR2) ....... . 12-13 12.5 Transmit Control Registers (XCR1 and XCR2) .
Page 12 Figures Figures 1−1 Conceptual Block Diagram of the McBSP ........2−1 McBSP Data Transfer Paths .
Page 13 Figures 5−3 McBSP Data Transfer in the 8-Partition Mode ........5−4 Activity on McBSP Pins for the Possible Values of XMCM .
Page 14 Figures 8−6 Register Bit Used to Choose One or Two Phases for the Transmit Frame ... . 8-10 8−7 Register Bits Used to Set the Transmit Word Length(s) ......8-11 8−8 Register Bits Used to Set the Transmit Frame Length...
Page 15 Tables Tables 1−1 McBSP Pins ..............2−1 McBSP Register Bits That Determine the Number of Phases, Words, and Bits Per Frame...
Page 16 Tables 7−22 Register Bits Used to Set the SRG Frame-Sync Period and Pulse Width ... . 7-29 7−23 Register Bits Used to Set the Receive Clock Mode ....... 7-31 7−24 Select Sources to Provide the Receive Clock Signal and the Effect on the...
Page 17 Tables 12−4 RCR2 Bit Descriptions ............12-16 12−5 XCR1 Bit Descriptions...
Page 18 Chapter 1 Introduction to the McBSP This chapter offers an introduction on multichannel buffered serial port (McBSP) for the TMS320C55x DSPs. Topic Page Introduction ..........Key Features of the McBSP .
Page 19: Introduction To The Mcbsp
Introduction Introduction / Key Features of the McBSP 1.1 Introduction The TMS320C55x DSPs provide multiple high-speed, multichannel buffered serial ports (McBSPs) that allow direct interface to other C55x DSPs, codecs, and other devices in a system. For the number of McBSPs available on a particular C55x device, see the device-specific data manual.
Page 20 Key Features of the McBSP A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits Note: A value of the chosen data size is referred to as a serial word or word throughout the McBSP documentation. Elsewhere, word is used to describe a 16-bit value.
Page 21: Block Diagram Of The Mcbsp
Á Á Á Á Á DMA controller Clock for McBSP operation † McBSP internal input clock: On TMS320VC5503/5507/5509 and TMS320VC5510 devices, this clock is the CPU clock. On TMS320VC5501 and TMS320VC5502 devices, this clock is the slow peripherals clock. Introduction to the McBSP SPRU592E...
Page 22 Block Diagram of the McBSP Data is communicated to devices interfaced with the McBSP via the data transmit (DX) pin for transmission and the data receive (DR) pin for reception. Control information in the form of clocking and frame synchronization is communicated via the following pins: CLKX (transmit clock), CLKR (receive clock), FSX (transmit frame sync), and FSR (receive frame sync).
Page 23: Mcbsp Pins
McBSP Pins 1.4 McBSP Pins Table 1−1 describes the McBSP interface pins. In the Possible States column, I = Input, O = Output, Z = High impedance. Table 1−1. McBSP Pins Possible States Possible Uses CLKR I/O/Z Supplying or reflecting the receive clock; supplying the input clock of the sample rate generator;...
Page 24 Chapter 2 McBSP Operation This chapter details the operation of the McBSP; the way the McBSP transmits or receives all data. Topic Page Data Transfer Process of a McBSP ......Companding (Compressing and Expanding) Data .
Page 25: Mcbsp Operation
Data Transfer Process of a McBSP 2.1 Data Transfer Process of a McBSP Figure 2−1 shows a diagram of the McBSP data transfer paths. McBSP receive operation is triple buffered, and transmit operation is double buffered. The use of registers varies depending on whether the defined length of each serial word fits in 16 bits.
Page 26: Data Transfer Process For Word Length Of 20, 24, Or 32 Bits
Data Transfer Process of a McBSP 2.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits If the word length is larger than 16 bits, two 16-bit registers are needed at each stage of the data transfer paths. The registers DRR2, RBR2, RSR2, DXR2, and XSR2 are needed to hold the most significant bits.
Page 27: Companding (Compressing And Expanding) Data
Companding (Compressing and Expanding) Data 2.2 Companding (Compressing and Expanding) Data Companding (COMpressing and exPANDing) hardware allows compression and expansion of data in either µ-law or A-law format. The companding standard employed in the United States and Japan is µ-law. The European companding standard is referred to as A-law.
Page 28: Capability To Compand Internal Data
Companding (Compressing and Expanding) Data Figure 2−3. µ-Law Transmit Data Companding Format 15−2 1−0 µ-law format in DXR1 Value For transmission using A-law compression, make sure the 13 data bits are left-justified in DXR1, with the remaining three low-order bits filled with 0s as shown in Figure 2−4.
Page 29: Reversing Bit Order: Option To Transfer Lsb First
Companding (Compressing and Expanding) Data The McBSP is enabled in digital loopback mode with companding appropriately enabled by RCOMPAND and XCOMPAND. Receive and transmit interrupts (RINT when RINTM = 00b and XINT when XINTM = 00b) or synchronization events (REVT and XEVT) allow synchronization of the CPU or the DMA controller to these conversions, respectively.
Page 30: Clocking And Framing Data
The maximum frequency for the McBSP on the TMS320VC5503/5507/5509 and TMS320VC5510 devices is 1/2 the CPU clock frequency. The maximum frequency for the McBSP on the TMS320VC5501 and TMS320VC5502 devices is 1/2 the frequency of the slow peripherals clock. For more...
Page 31: Frames And Frame Synchronization
Clocking and Framing Data During transmission, XSR does not accept new data from DXR until a full serial word has been passed from XSR to the DX pin. In the following example, an 8-bit word size was defined (see bits 7 through 0 of word B being transferred).
Page 32: Detecting Frame-Sync Pulses, Even In The Reset State
Clocking and Framing Data 2.3.4 Detecting Frame-Sync Pulses, Even in the Reset State The McBSP can send receive and transmit interrupts to the CPU to indicate specific events in the McBSP. To facilitate detection of frame synchronization, these interrupts can be sent in response to frame-sync pulses. Set the appropriate interrupt mode bits to 10b (for reception, RINTM = 10b;...
Page 33: Mcbsp Operating At Maximum Packet Frequency
(CLKX). Note: On the TMS320VC5501 and TMS320VC5502 devices, if a 0-bit delay and an external clock are used, the transfer shown in Figure 2−6 can only be achieved if the frame-sync ignore bit is set to 1. If the frame-sync ignore bit is 0, an additional clock cycle is required between frames.
Page 34: Frame Phases
Frame Phases 2.4 Frame Phases The McBSP allows you to configure each frame to contain one or two phases. The number of words per frame, and the number of bits per word, can be specified differently for each of the two phases of a frame, allowing greater flexibility in structuring data transfers.
Page 35: Dual-Phase Frame Example
Frame Phases (R/X)WDLEN1 = 000b: 8-bit word length (R/X)FRLEN2 and (R/X)WDLEN2 are ignored CLK(X/R)P = 0: Receive data clocked on falling edge; transmit data clocked on rising edge FS(R/X)P = 0: Active-high frame-sync signals (R/X)DATDLY = 01b: 1-bit data delay Figure 2−7.
Page 36: Implementing The Ac97 Standard With A Dual-Phase Frame
Frame Phases 2.4.4 Implementing the AC97 Standard With a Dual-Phase Frame Figure 2−9 shows an example of the Audio Codec ‘97 (AC97) standard, which uses the dual-phase frame feature. Notice that words, not individual bits, are shown on the D(R/X) signal. The first phase (P1) consists of a single 16-bit word.
Page 37: Timing Of An Ac97-Standard Data Transfer Near Frame Synchronization
PxWyBz = Phase x Word y Bit z Note: On the TMS320VC5501 and TMS320VC5502 devices, if a 0-bit delay and an external clock are used, the transfer shown in Figure 2−9 can only be achieved if the frame-sync ignore bit is set to 1. If the frame-sync ignore bit is 0, an additional clock cycle is required between frames.
Page 38: Mcbsp Reception
McBSP Reception 2.5 McBSP Reception This section explains the fundamental process of reception in the McBSP. For more details on how to configure the receiver, see Chapter 7, Receiver Configuration. Figure 2−11 and Figure 2−12 show how reception occurs in the McBSP. Figure 2−11 shows the physical path for the data.
Page 39 McBSP Reception 4) When a full word is received, the McBSP copies the contents of the receive shift register(s) to the receive buffer register(s), provided that RBR1 is not full with previous data. If the word length is 16 bits or smaller, only RBR1 is used. If the word length is larger than 16 bits, RBR2 and RBR1 are used, and RBR2 contains the most significant bits.
Page 40: Mcbsp Transmission Physical Data Path
McBSP Transmission 2.6 McBSP Transmission This section explains the fundamental process of transmission in the McBSP. For details about how to program the McBSP transmitter, see Chapter 8, Transmitter Configuration. Figure 2−13 and Figure 2−14 show how transmission occurs in the McBSP. Figure 2−13 shows the physical path for the data.
Page 41 McBSP Transmission 2) When new data arrives in DXR1, the McBSP copies the content of the data transmit register(s) to the transmit shift register(s). In addition, the transmit ready bit (XRDY) is set. This indicates that the transmitter is ready to accept new data from the CPU or the DMA controller.
Page 42: Interrupts And Dma Events Generated By A Mcbsp
Interrupts and DMA Events Generated by a McBSP 2.7 Interrupts and DMA Events Generated by a McBSP The McBSP sends notification of important events to the CPU and the DMA controller via the internal signals shown in Table 2−2. Table 2−2. Interrupts and DMA Events Generated by a McBSP Internal Signal Description RINT...
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Page 44 Chapter 3 Sample Rate Generator of the McBSP This chapter gives information on the use of the sample rate generator to drive clocking, and provides the appropriate clocking examples for support. Topic Page Sample Rate Generator ........Clock Generation in the Sample Rate Generator .
Page 45: Conceptual Block Diagram Of The Sample Rate Generator
GSYNC † On TMS320VC5501 and TMS320VC5502 devices, the polarity of the sample rate generator input clock (CLKSRG) is always positive (rising edge), regardless of CLKRP or CLKXP. ‡ McBSP internal input clock: On TMS320VC5503/5507/5509 and TMS320VC5510 devices, this clock is the CPU clock. On TMS320VC5501 and TMS320VC5502 devices, this clock is the slow peripherals clock.
Page 46 (CLKXP of PCR, CLKRP of PCR, or CLKSP of SRGR2). Note: On TMS320VC5501 and TMS320VC5502 devices, the polarity of the sample rate generator input clock is always positive (rising edge), regardless of CLKRP or CLKXP.
Page 47: Effects Of Dlb And Clkstp On Clock Modes
SRGR2. Note: The clock synchronization provided through the GSYNC bit is not supported on TMS320VC5501 and TMS320VC5502 devices. 3.2 Clock Generation in the Sample Rate Generator The sample rate generator can produce a clock signal (CLKG) for use by the receiver, the transmitter, or both.
Page 48: Choosing An Input Clock For The Sample Rate Generator With The Sclkme And
The maximum frequency for the McBSP on the TMS320VC5503/5507/5509 and TMS320VC5510 devices is 1/2 the CPU clock frequency. The maximum frequency for the McBSP on the TMS320VC5501 and TMS320VC5502 devices is 1/2 the frequency of the slow peripherals clock. For more...
Page 49: Possible Inputs To The Sample Rate Generator And The Polarity Bits
§ CLKSP † On TMS320VC5501 and TMS320VC5502 devices, the polarity of the sample rate generator input clock (CLKSRG) is always positive (rising edge), regardless of CLKRP or CLKXP. ‡ McBSP internal input clock: On TMS320VC5503/5507/5509 and TMS320VC5510 devices, this clock is the CPU clock. On TMS320VC5501 and TMS320VC5502 devices, this clock is the slow peripherals clock.
Page 50: Falling Edge
† Not all C55x devices have a CLKS pin; check the device-specific data manual. ‡ On TMS320VC5501 and TMS320VC5502 devices, the polarity of the sample rate generator input clock is always positive (rising edge), regardless of CLKRP or CLKXP. 3.2.3...
Page 51 The maximum frequency for the McBSP on the TMS320VC5503/5507/5509 and TMS320VC5510 devices is 1/2 the CPU clock frequency. The maximum frequency for the McBSP on the TMS320VC5501 and TMS320VC5502 devices is 1/2 the frequency of the slow peripherals clock. For more...
Page 52: Frame Sync Generation In The Sample Rate Generator
Frame Sync Generation in the Sample Rate Generator 3.3 Frame Sync Generation in the Sample Rate Generator The sample rate generator can produce a frame-sync signal (FSG) for use by the receiver, the transmitter, or both. If you want the receiver to use FSG for frame synchronization, set FSRM = 1. (When FSRM = 0, receive frame synchronization is supplied via the FSR pin.) If you want the transmitter to use FSG for frame synchronization, you must set:...
Page 53: Synchronizing Sample Rate Generator Outputs To An External Clock
FSG is determined by the arrival of the next frame-sync pulse on the FSR pin. If GSYNC = 0, CLKG runs freely and is not resynchronized, and the frame-sync period on FSG is determined by FPER. This clock synchronization is not supported on TMS320VC5501 and TMS320VC5502 devices. 3.4.1 Synchronization Examples Figure 3−3 and Figure 3−4 show the clock and frame-synchronization...
Page 54: Clkg Synchronization And Fsg Generation When Gsync = 1, Clkgdv = 1, And Clks Provides The Sample Rate Generator Input Clock
Synchronizing Sample Rate Generator Outputs to an External Clock Figure 3−3. CLKG Synchronization and FSG Generation When GSYNC = 1, CLKGDV = 1, and CLKS Provides the Sample Rate Generator Input Clock CLKS (CLKSP=1) CLKS (CLKSP=0) FSR external (FSRP=0) FSR external (FSRP=1) CLKG (No need to...
Page 55: Reset And Initialization Procedure For The Sample Rate Generator
Reset and Initialization Procedure for the Sample Rate Generator 3.5 Reset and Initialization Procedure for the Sample Rate Generator To reset and initialize the sample rate generator: 1) Place the sample rate generator in reset. During a DSP reset, the sample rate generator, the receiver, and the transmitter reset bits (GRST, RRST, and XRST) are automatically forced to 0.
Page 56 Reset and Initialization Procedure for the Sample Rate Generator 4) If necessary, enable the receiver and/or the transmitter. If necessary, remove the receiver and/or transmitter from reset by setting RRST and/or XRST = 1. 5) If necessary, enable the frame-sync logic of the sample rate generator.
Page 57: St-Bus And Mvip Clocking Example
Sample Rate Generator Clocking Examples 3.6 Sample Rate Generator Clocking Examples This section shows three examples of using the sample rate generator to clock data during transmission and reception. 3.6.1 Double-Rate ST-Bus Clock Figure 3−5 shows McBSP configuration to be compatible with the Mitel ST-Bus.
Page 58: Single-Rate Clock Example
(R/X)WDLEN2 are ignored RDATDLY/XDATDLY = 0: No data delay The clock synchronization provided through the GSYNC bit is not supported on TMS320VC5501 and TMS320VC5502 devices. 3.6.2 Single-Rate ST-Bus Clock The example in Figure 3−6 is the same as the double-rate ST-bus clock example in section 3.6.1 except that:...
Page 59: Double-Rate Clock Example
Sample Rate Generator Clocking Examples 3.6.3 Other Double-Rate Clock The example in Figure 3−7 is the same as the double-rate ST-bus clock example in section 3.6.1 except that: CLKSP = 0: Rising edge of CLKS generates CLKG and thus CLK(R/X) CLKGDV = 1: Frequency of CLKG (and thus internal CLKR and internal CLKX) is half CLKS frequency FSRM/FSXM = 0: Frame synchronization is externally generated.
Page 60 Chapter 4 McBSP Exception/Error Conditions This chapter provides a detailed explanation and listing of exception or error conditions associated with the McBSP. Topic Page McBSP Exception/Error Conditions ......Overrun in the Receiver .
Page 61: Mcbsp Exception/Error Conditions
McBSP Exception/Error Conditions 4.1 McBSP Exception/Error Conditions There are five serial port events that may constitute a system error: Receiver Overrun (RFULL = 1 in SPCR1). This occurs when DRR1 has not been read since the last RBR-to-DRR copy. Consequently, the receiver does not copy a new word from the RBR(s) to the DRR(s), and the RSR(s) are now full with another new word shifted in from DR.
Page 62: Overrun In The Receiver
Overrun in the Receiver 4.2 Overrun in the Receiver RFULL = 1 in SPCR1 indicates that the receiver has experienced overrun and is in an error condition. RFULL is set when all of the following conditions are met: 1) DRR1 has not been read since the last RBR-to-DRR copy (RRDY = 1). 2) RBR1 is full and an RBR-to-DRR copy has not occurred.
Page 63: Overrun In The Mcbsp Receiver
Overrun in the Receiver Figure 4−1. Overrun in the McBSP Receiver CLKR Á Á Á Á Á Á Á Á Á Á Á Á No RSR1 to RBR1 copy(C) Á Á RRDY RBR1 to DRR1 copy(A) No read from DRR1(A) No read from DRR1(A) No RBR1 to DRR1 copy(B) RFULL...
Page 64: Unexpected Receive Frame-Sync Pulse
Unexpected Receive Frame-Sync Pulse 4.3 Unexpected Receive Frame-Sync Pulse This section discusses how the McBSP responds to all receive frame-sync pulses, including an unexpected pulse. It also provides examples of a frame-sync error and an example of how to prevent such an error. 4.3.1 Possible Responses to Receive Frame-Sync Pulses Figure 4−3 shows the decision tree that the receiver uses to handle all...
Page 65 Unexpected Receive Frame-Sync Pulse Any one of three cases can occur: Case 1: Unexpected internal FSR pulses with RFIG = 1 in RCR2. Receive frame-sync pulses are ignored, and the reception continues. Case 2: Normal serial port reception. Reception continues normally because the frame-sync pulse is not unexpected.
Page 66: An Unexpected Frame-Sync Pulse During A Mcbsp Reception
Unexpected Receive Frame-Sync Pulse Figure 4−4. An Unexpected Frame-Sync Pulse During a McBSP Reception CLKR Unexpected frame synchronization Á Á Á Á Á Á RBR1 to DRR1(B) RRDY RBR1 to DRR1 copy(A) Read from DRR1(A) RBR1 to DRR1 copy(C) Read from DRR1(C) RSYNCERR 4.3.3 Preventing Unexpected Receive Frame-Sync Pulses...
Page 67: Data In The Mcbsp Transmitter Overwritten And, Therefore, Not Transmitted
Overwrite in the Transmitter 4.4 Overwrite in the Transmitter After the CPU or the DMA controller writes data to the DXR(s), the transmitter must then copy that data to the XSR(s) and then shift each bit from the XSR(s) to the DX pin. If new data is written to the DXR(s) before the previous data is copied to the XSR(s), the previous data in the DXR(s) is overwritten and thus lost.
Page 68: Underflow In The Transmitter
Underflow in the Transmitter 4.5 Underflow in the Transmitter The McBSP indicates a transmitter empty (or underflow) condition by clearing the XEMPTY bit in SPCR2. Either of the following events activates XEMPTY (XEMPTY = 0): DXR1 has not been loaded since the last DXR-to-XSR copy, and all bits of the data word in the XSR(s) have been shifted out on the DX pin.
Page 69: Underflow During Mcbsp Transmission
Underflow in the Transmitter 4.5.1 Example of the Underflow Condition Figure 4−7 shows an underflow condition. After B is transmitted, DXR1 is not reloaded before the subsequent frame-sync pulse. Thus, B is again transmitted on DX. Figure 4−7. Underflow During McBSP Transmission CLKX Á...
Page 70: Possible Responses To Transmit Frame-Sync Pulses
Unexpected Transmit Frame-Sync Pulse 4.6 Unexpected Transmit Frame-Sync Pulse This section discusses how the McBSP responds to any transmit frame-sync pulses, including an unexpected pulse. It also provides examples of a frame-sync error and an example of how to prevent such an error. 4.6.1 Possible Responses to Transmit Frame-Sync Pulses Figure 4−9 shows the decision tree that the transmitter uses to handle all...
Page 71 Unexpected Transmit Frame-Sync Pulse Any one of three cases can occur: Case 1: Unexpected internal FSX pulses with XFIG = 1 in XCR2. Unexpected transmit frame-sync pulses are ignored, and the transmission continues. Case 2: Normal serial port transmission. Transmission continues normally because the frame-sync pulse is not unexpected.
Page 72: An Unexpected Frame-Sync Pulse During A Mcbsp Transmission
Unexpected Transmit Frame-Sync Pulse Figure 4−10. An Unexpected Frame-Sync Pulse During a McBSP Transmission CLKX Unexpected frame synchronization Á Á Á Á Á Á XRDY DXR1 to XSR1 copy(B) Write to DXR1(C) DXR1 to XSR1 (C) Write to DXR1(D) XSYNCERR 4.6.3 Preventing Unexpected Transmit Frame-Sync Pulses Each frame transfer can be delayed by 0, 1, or 2 CLKX cycles, depending on...
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Page 74 Chapter 5 Multichannel Selection Modes This chapter defines and provides the functions and all related information concerning the multichannel selection modes. Topic Page Channels, Blocks, and Partitions ....... Multichannel Selection .
Page 75 Channels, Blocks, and Partitions 5.1 Channels, Blocks, and Partitions A McBSP channel is a time slot for shifting in/out the bits of one serial word. Each McBSP supports up to 128 channels for reception and 128 channels for transmission. In the receiver and in the transmitter, the 128 available channels are divided into eight blocks that each contain 16 contiguous channels: Block 0: Channels 0–15 Block 4: Channels 64–79...
Page 76 Multichannel Selection 5.2 Multichannel Selection When a McBSP uses a time-division multiplexed (TDM) data stream while communicating with other McBSPs or serial devices, the McBSP may need to receive and/or transmit on only a few channels. To save memory and bus bandwidth, you can use a multichannel selection mode to prevent data flow in some of the channels.
Page 77: Multichannel Selection
TMS320VC5501/02 McBSP transmitter will ignore the first frame-sync pulse after it is taken out of reset. The transmitter will transmit only on the second frame-sync pulse. The receiver will shift in data on the first frame-sync pulse regardless of whether it is generated internally or externally.
Page 78: Selection Mode
Using Two Partitions 5.4 Using Two Partitions For multichannel selection operation in the receiver and/or the transmitter, you can use two partitions or eight partitions. If you choose the 2-partition mode (RMCME = 0 for reception, XMCME = 0 for transmission), McBSP channels are activated using an alternating scheme.
Page 79: Alternating Between The Channels Of Partition A And The Channels Of Partition B
Using Two Partitions Figure 5−1 shows an example of alternating between the channels of partition A and the channels of partition B. Channels 0-15 have been assigned to partition A, and channels 16-31 have been assigned to partition B. In response to a frame-sync pulse, the McBSP begins a frame transfer with partition A and then alternates between partitions B and A until the complete frame is transferred.
Page 80: Reassigning Channel Blocks Throughout A Mcbsp Data Transfer
Using Two Partitions Figure 5−2 shows an example of reassigning channels throughout a data transfer. In response to a frame-sync pulse, the McBSP alternates between partitions A and B. Whenever partition B is active, the CPU changes the block assignment for partition A. Whenever, partition A is active, the CPU changes the block assignment for partition B.
Page 81: Receive Channel Assignment And Control When Eight Receive Partitions Are Used
Using Eight Partitions 5.5 Using Eight Partitions For multichannel selection operation in the receiver and/or the transmitter, you can use eight partitions or two partitions. If you choose the 8-partition mode (RMCME = 1 for reception, XMCME = 1 for transmission), McBSP partitions are activated in the following order: A, B, C, D, E, F, G, H.
Page 82: Mcbsp Data Transfer In The 8-Partition Mode
Using Eight Partitions Table 5−2. Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used Transmit Assigned Block of Register Used For Partition Transmit Channels Channel Control Block 0: channels 0 through 15 XCERA Block 1: channels 16 through 31 XCERB Block 2: channels 32 through 47 XCERC...
Page 83: Receive Multichannel Selection Mode
Receive Multichannel Selection Mode 5.6 Receive Multichannel Selection Mode The RMCM bit of MCR1 determines whether all channels or only selected channels are enabled for reception. When RMCM = 0, all 128 receive channels are enabled and cannot be disabled. When RMCM = 1, the receive multichannel selection mode is enabled.
Page 84: Selecting A Transmit Multichannel Selection Mode With The Xmcm Bits
Transmit Multichannel Selection Mode 5.7 Transmit Multichannel Selection Mode The XMCM bits of XCR2 determine whether all channels or only selected channels are enabled and unmasked for transmission. The McBSP has three transmit multichannel selection modes (XMCM = 01b, XMCM = 10b, and XMCM = 11b), which are described in the following table: Table 5−3.
Page 85 Transmit Multichannel Selection Mode As an example of how the McBSP behaves in a transmit multichannel selection mode, suppose that XMCM = 01b (all channels disabled unless individually enabled) and that you have enabled only channels 0, 15, and 39. Suppose also that the frame length is 40.
Page 86: Activity On Mcbsp Pins For The Possible Values Of Xmcm
Transmit Multichannel Selection Mode Disabled channel A channel that is not enabled. A disabled channel is also masked. Because no DXR-to-XSR copy occurs, the XRDY bit of SPCR2 is not set. Therefore, no DMA synchronization event (XEVT) is generated, and if the transmit interrupt mode depends on XRDY (XINTM = 00b in SPCR2), no interrupt is generated.
Page 87 Transmit Multichannel Selection Mode Figure 5−4. Activity on McBSP Pins for the Possible Values of XMCM (Continued) (b) XMCM = 01b, XPABLK = 00b, XCERA = 000Ah: Only channels 1 and 3 enabled and unmasked Internal FSX Á Á Á Á...
Page 88: Using Interrupts Between Block Transfers
Using Interrupts Between Block Transfers 5.8 Using Interrupts Between Block Transfers When a multichannel selection mode is used, an interrupt request can be sent to the CPU at the end of every 16-channel block (at the boundary between partitions and at the end of the frame). In the receive multichannel selection mode, a receive interrupt (RINT) request is generated at the end of each block transfer if RINTM = 01b.
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Page 90 Chapter 6 SPI Operation Using the Clock Stop Mode This chapter describes how the McBSP can communicate with one or more devices using the SPI protocol. Topic Page SPI Protocol ..........Clock Stop Mode .
Page 91: Typical Spi Interface
SPI Protocol 6.1 SPI Protocol The SPI protocol is a master-slave configuration with one master device and one or more slave devices. The interface consists of the following four signals: Serial data input (also referred to as Master In − Slave Out, or MISO) Serial data output (also referred to as Master Out −...
Page 92 Clock Stop Mode 6.2 Clock Stop Mode The clock stop mode of the McBSP provides compatibility with the SPI protocol. When the McBSP is configured in clock stop mode, the transmitter and receiver are internally synchronized, so that the McBSP functions as an SPI master or slave device.
Page 93: Bits Used To Enable And Configure The Clock Stop Mode
Bits Used to Enable and Configure the Clock Stop Mode 6.3 Bits Used to Enable and Configure the Clock Stop Mode The bits required to configure the McBSP as an SPI device are introduced in Table 6−1. Table 6−2 shows how the various combinations of the CLKSTP bit and the polarity bits CLKXP and CLKRP create four possible clock stop mode configurations.
Page 94: Effects Of Clkstp, Clkxp, And Clkrp On The Clock Scheme
Bits Used to Enable and Configure the Clock Stop Mode Table 6−2. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme Bit Settings Clock Scheme CLKSTP = 00b or 01b Clock stop mode disabled. Clock enabled for non-SPI CLKXP = 0 or 1 mode.
Page 95: Spi Transfer With Clkstp = 10B (No Clock Delay), Clkxp = 0, Clkrp
Clock Stop Mode Timing Diagrams 6.4 Clock Stop Mode Timing Diagrams The timing diagrams for the four possible clock stop mode configurations are shown here. Notice that the frame-synchronization signal used in clock stop mode is active throughout the entire transmission as a slave-enable signal. Although the timing diagrams show 8-bit transfers, the packet length can be set to 8, 12, 16, 20, 24, or 32 bits per packet.
Page 96: Spi Transfer With Clkstp = 10B (No Clock Delay), Clkxp = 1, Clkrp
Clock Stop Mode Timing Diagrams Figure 6−4. SPI Transfer With CLKSTP = 10b (no clock delay), CLKXP = 1, CLKRP = 0 Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á CLKX/SCK Á...
Page 97 Procedure for Configuring a McBSP for SPI Operation 6.5 Procedure for Configuring a McBSP for SPI Operation To configure the McBSP for SPI master or slave operation: 1) Place the transmitter and receiver in reset. Clear the transmitter reset bit (XRST = 0) in SPCR2, to reset the transmitter.
Page 98 Procedure for Configuring a McBSP for SPI Operation 6) If necessary, enable the frame-sync logic of the sample rate generator. After the required data acquisition setup is done (DXR[1/2] is loaded with data), set FRST = 1 if an internally generated frame-sync pulse is required (that is, if the McBSP is the SPI master).
Page 99: Mcbsp As The Spi Master
McBSP as the SPI Master 6.6 McBSP as the SPI Master An SPI interface with the McBSP used as the master is shown in Figure 6−6. When the McBSP is configured as a master, the transmit output signal (DX) is used as the MOSI signal of the SPI protocol, and the receive input signal (DR) is used as the MISO signal.
Page 100: Bit Values Required To Configure The Mcbsp As An Spi Master
McBSP as the SPI Master Table 6−3. Bit Values Required to Configure the McBSP as an SPI Master Required Bit Setting Description CLKSTP = 10b or 11b The clock stop mode (without or with a clock delay) is selected. CLKXP = 0 or 1 The polarity of CLKX as seen on the CLKX pin is positive (CLKXP = 0) or negative (CLKXP = 1).
Page 101 McBSP as the SPI Master The McBSP can also provide a slave-enable signal (SS) on the FSX pin. If a slave-enable signal is required, the FSX pin must be configured as an output, and the transmitter must be configured so that a frame-sync pulse is generated automatically each time a packet is transmitted (FSGM = 0).
Page 102: Mcbsp As An Spi Slave
McBSP as an SPI Slave 6.7 McBSP as an SPI Slave An SPI interface with the McBSP used as a slave is shown in Figure 6−7. When the McBSP is configured as a slave, DX is used as the MISO signal, and DR is used as the MOSI signal.
Page 103: Bit Values Required To Configure The Mcbsp As An Spi Slave
McBSP as an SPI Slave Table 6−4. Bit Values Required to Configure the McBSP as an SPI Slave Required Bit Setting Description CLKSTP = 10b or 11b The clock stop mode (without or with a clock delay) is selected. CLKXP = 0 or 1 The polarity of CLKX as seen on the CLKX pin is positive (CLKXP = 0) or negative (CLKXP = 1).
Page 104 McBSP as an SPI Slave The McBSP requires an active edge of the slave-enable signal on the FSX input for each transfer. This means that the master device must assert the slave-enable signal at the beginning of each transfer, and deassert the signal after the completion of each packet transfer;...
Page 105 This page is intentionally left blank. 6-16 SPI Operation Using the Clock Stop Mode SPRU592E...
Page 106 Chapter 7 Receiver Configuration This chapter describes how to configure the McBSP receiver. Topic Page Configuring the McBSP Receiver ....... Programming McBSP Registers for Desired Receiver Operation .
Page 107 Configuring the McBSP Receiver 7.1 Configuring the McBSP Receiver You must perform the following three steps to configure the McBSP receiver. 1) Place the McBSP/receiver in reset 2) Program the McBSP registers for the desired receiver operation 3) Take the receiver out of reset Receiver Configuration SPRU592E...
Page 108 Programming McBSP Registers for Desired Receiver Operation 7.2 Programming McBSP Registers for Desired Receiver Operation The following is a list of important tasks to be performed when you are configuring the McBSP receiver. Each task corresponds to one or more McBSP register bit fields.
Page 109: Register Bits Used To Reset Or Enable The Mcbsp Receiver
Resetting and Enabling the Receiver 7.3 Resetting and Enabling the Receiver The first step of the receiver configuration procedure is to reset the receiver, and the last step is to enable the receiver (to take it out of reset). Figure 7−1 and Table 7−1 describe the bits used for both of these steps.
Page 110: Reset State Of Each Mcbsp Pin
Resetting and Enabling the Receiver 7.3.1 Reset Considerations The serial port can be reset in the following two ways: 1) A DSP reset (RESET signal driven low) places the receiver, transmitter, and sample rate generator in reset. When the device reset is removed (RESET signal driven high), GRST = FRST = RRST = XRST = 0, keeping the entire serial port in the reset state.
Page 111: Register Bit Used To Set Receiver Pins To Operate As Mcbsp Pins
Setting the Receiver Pins to Operate as McBSP Pins 7.4 Setting the Receiver Pins to Operate as McBSP Pins The RIOEN bit, shown in Figure 7−2 and described in Table 7−3, determines whether the receiver pins are McBSP pins or general-purpose I/O pins. Figure 7−2.
Page 112: Register Bit Used To Enable/Disable The Digital Loopback Mode
Enabling/Disabling the Digital Loopback Mode 7.5 Enabling/Disabling the Digital Loopback Mode The DLB bit determines whether the digital loopback mode is on. DLB is shown in Figure 7−3 and described in Table 7−4. Figure 7−3. Register Bit Used to Enable/Disable the Digital Loopback Mode SPCR1 R/W-0 Legend: R = Read;...
Page 113: Register Bits Used To Enable/Disable The Clock Stop Mode
Enabling/Disabling the Clock Stop Mode 7.6 Enabling/Disabling the Clock Stop Mode The CLKSTP bits determine whether the clock stop mode is on and whether a clock delay is selected. CLKSTP is shown in Figure 7−4 and described in Table 7−6. Figure 7−4.
Page 114: Register Bit Used To Enable/Disable The Receive Multichannel Selection Mode
Enabling/Disabling the Receive Multichannel Selection Mode 7.7 Enabling/Disabling the Receive Multichannel Selection Mode The RMCM bit determines whether the receive multichannel selection mode is on. RMCM is shown in Figure 7−5 and described in Table 7−7. Figure 7−5. Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode MCR1 RMCM R/W-0...
Page 115: Register Bit Used To Choose One Or Two Phases For The Receive Frame
Choosing One or Two Phases for the Receive Frame 7.8 Choosing One or Two Phases for the Receive Frame The RPHASE bit (see Figure 7−6 and Table 7−8) determines whether the receive data frame has one or two phases. Figure 7−6. Register Bit Used to Choose One or Two Phases for the Receive Frame RCR2 RPHASE R/W-0...
Page 116: Register Bits Used To Set The Receive Word Length(S)
Setting the Receive Word Length(s) 7.9 Setting the Receive Word Length(s) The RWDLEN1 and RWDLEN2 fields (see Figure 7−7 and Table 7−9) determine how many bits are in each serial word in phase 1 and in phase 2, respectively, of the receive data frame. Figure 7−7.
Page 117 Setting the Receive Word Length(s) 7.9.1 About the Word Length Bits Each frame can have one or two phases, depending on the value that you load into the RPHASE bit. If a single-phase frame is selected, RWDLEN1 selects the length for every serial word received in the frame and RWDLEN2 is ignored.
Page 118: Register Bits Used To Set The Receive Frame Length
Setting the Receive Frame Length 7.10 Setting the Receive Frame Length The RFRLEN1 and RFRLEN2 bit fields (see Figure 7−8 and Table 7−10) determine how many serial words are in phase 1 and in phase 2, respectively, of the receive data frame. Figure 7−8.
Page 119: How To Calculate The Length Of The Receive Frame
Setting the Receive Frame Length 7.10.1 About the Selected Frame Length The receive frame length is the number of serial words in the receive frame. Each frame can have one or two phases, depending on the value that you load into the RPHASE bit.
Page 120: Register Bit Used To Enable/Disable The Receive Frame-Sync Ignore Function
Enabling/Disabling the Receive Frame-Sync Ignore Function 7.11 Enabling/Disabling the Receive Frame-Sync Ignore Function The RFIG bit (see Figure 7−9 and Table 7−12) controls the receive frame-sync ignore function. Figure 7−9. Register Bit Used to Enable/Disable the Receive Frame-Sync Ignore Function RCR2 RFIG R/W-0...
Page 121: Register Bits Used To Set The Receive Companding Mode
Setting the Receive Companding Mode 7.12 Setting the Receive Companding Mode The RCOMPAND bits (see Figure 7−10 and Table 7−13) determine whether companding or another data transfer option is chosen for McBSP reception. Figure 7−10. Register Bits Used to Set the Receive Companding Mode RCR2 RCOMPAND R/W-00...
Page 122: Register Bits Used To Set The Receive Data Delay
Setting the Receive Data Delay 7.13 Setting the Receive Data Delay The RDATDLY bits (see Figure 7−11 and Table 7−14) determine the length of the data delay for the receive frame. Figure 7−11.Register Bits Used to Set the Receive Data Delay RCR2 RDATDLY R/W-00...
Page 123: Range Of Programmable Data Delay
Setting the Receive Data Delay Figure 7−12. Range of Programmable Data Delay CLK(R/X) FS(R/X) 0-bit delay Á Á D(R/X) Data delay 0 Á Á 1-bit delay Á D(R/X) Data delay 1 Á 2-bit delay D(R/X) Á Data delay 2 Á 7.13.2 0-Bit Data Delay Normally, a frame-sync pulse is detected or sampled with respect to an edge of internal serial clock CLK(R/X).
Page 124 Setting the Receive Data Delay Figure 7−13. 2-Bit Data Delay Used to Skip a Framing Bit CLKR 2-bit delay Á Framing bit Á SPRU592E Receiver Configuration 7-19...
Page 125: Register Bits Used To Set The Receive Sign-Extension And Justification Mode
Setting the Receive Sign-Extension and Justification Mode 7.14 Setting the Receive Sign-Extension and Justification Mode The RJUST bits (see Figure 7−14 and Table 7−15) determine whether data received by the McBSP is sign extended and how it is justified. Figure 7−14. Register Bits Used to Set the Receive Sign-Extension and Justification Mode SPCR1 13 12 RJUST...
Page 126: Example: Use Of Rjust Field With 20-Bit Data Value 0Xabcde
Setting the Receive Sign-Extension and Justification Mode Table 7−17. Example: Use of RJUST Field With 20-Bit Data Value 0xABCDE Value in Value in DRR2 DRR1 RJUST Justification Extension Right Zero fill MSBs 000Ah BCDEh Right Sign extend data into FFFAh BCDEh MSBs Left...
Page 127: Register Bits Used To Set The Receive Interrupt Mode
Setting the Receive Interrupt Mode 7.15 Setting the Receive Interrupt Mode The RINTM bits (see Figure 7−15 and Table 7−18) determine which event generates a receive interrupt request to the CPU. Figure 7−15. Register Bits Used to Set the Receive Interrupt Mode SPCR1 RINTM R/W-00...
Page 128: Register Bits Used To Set The Receive Frame Sync Mode
Receive frame synchronization is supplied by the sample rate generator. FSR is an output pin reflecting internal FSR, except when GSYNC = 1 in SRGR2. † The clock synchronization provided through the GSYNC bit is not supported on TMS320VC5501 and TMS320VC5502 devices. SPRU592E Receiver Configuration...
Page 129 (CLKR) and the internal receive frame-synchronization signal (FSR) internally connected to their transmit counterparts, CLKX and FSX. † The clock synchronization provided through the GSYNC bit is not supported on TMS320VC5501 and TMS320VC5502 devices. 7-24 Receiver Configuration SPRU592E...
Page 130: The Effect On The Fsr Pin
Receive (same transmit) frame synchronization is inverted as determined by FSRP before being driven out on the FSR pin. † The clock synchronization provided through the GSYNC bit is not supported on TMS320VC5501 and TMS320VC5502 devices. SPRU592E Receiver Configuration 7-25...
Page 131: Register Bit Used To Set Receive Frame-Sync Polarity
Setting the Receive Frame-Sync Polarity 7.17 Setting the Receive Frame-Sync Polarity The FSRP bit (see Figure 7−17 and Table 7−21) determines whether frame-synchronization (frame-sync) pulses are active high or active low on the FSR pin. Figure 7−17. Register Bit Used to Set Receive Frame-Sync Polarity FSRP R/W-0 Legend: R = Read;...
Page 132 Setting the Receive Frame-Sync Polarity FSRP, FSXP, CLKRP, and CLKXP in the pin control register (PCR) configure the polarities of the FSR, FSX, CLKR, and CLKX signals, respectively. All frame-sync signals (internal FSR, internal FSX) that are internal to the serial port are active high.
Page 133: Data Clocked Externally Using A Rising Edge And Sampled By The Mcbsp Receiver On A
Setting the Receive Frame-Sync Polarity Figure 7−18. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge Internal CLKR Data setup Data hold 7-28 Receiver Configuration SPRU592E...
Page 134: Register Bits Used To Set The Srg Frame-Sync Period And Pulse Width
Setting the SRG Frame-Sync Period and Pulse Width 7.18 Setting the SRG Frame-Sync Period and Pulse Width The FPER and FWID fields, shown in Figure 7−19 and described in Table 7−22, are used to set the SRG frame-sync period and pulse width. Figure 7−19.
Page 135: Frame Of Period 16 Clkg Periods And Active Width Of 2 Clkg Periods
Setting the SRG Frame-Sync Period and Pulse Width 7.18.1 About the Frame-Sync Period and the Frame-Sync Pulse Width The sample rate generator can produce a clock signal, CLKG, and a frame-sync signal, FSG. If the sample rate generator is supplying receive or transmit frame synchronization, you must program the bit fields FPER and FWID.
Page 136: Register Bits Used To Set The Receive Clock Mode
Setting the Receive Clock Mode 7.19 Setting the Receive Clock Mode The bits shown in Figure 7−21 and described in Table 7−23 determine the source for receive clock and the function of the CLKR pin. Figure 7−21. Register Bits Used to Set the Receive Clock Mode CLKRM R/W-0 SPCR1...
Page 137 Setting the Receive Clock Mode Table 7−23. Register Bits Used to Set the Receive Clock Mode (Continued) Register Name Function SPCR1 12-11 CLKSTP Clock Stop Mode CLKSTP = 0Xb Clock stop mode disabled; normal clocking for non-SPI mode. CLKSTP = 10b Clock stop mode enabled, without clock delay.
Page 138 Setting the Receive Clock Mode Table 7−24. Select Sources to Provide the Receive Clock Signal and the Effect on the CLKR Pin DLB in CLKRM in SPCR1 Source of Receive Clock CLKR Pin Status The CLKR pin is an input driven by an Input external clock.
Page 139: Register Bit Used To Set Receive Clock Polarity
Setting the Receive Clock Polarity 7.20 Setting the Receive Clock Polarity The CLKRP bit (see Figure 7−22 and Table 7−25) determines the receive clock polarity. Figure 7−22. Register Bit Used to Set Receive Clock Polarity CLKRP R/W-0 Legend: R = Read; W = Write; -n = Value after reset Table 7−25.
Page 140 Setting the Receive Clock Polarity When FSR and FSX are outputs, implying that they are driven by the sample rate generator, they are generated (transition to their active state) on the rising edge of internal clock, CLK(R/X). Similarly, data on the DX pin is output on the rising edge of internal CLKX.
Page 141: Data Clocked Externally Using A Rising Edge And Sampled By The Mcbsp Receiver On A
Setting the Receive Clock Polarity Figure 7−23. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge Internal CLKR Data setup Data hold 7-36 Receiver Configuration SPRU592E...
Page 142: Register Bits Used To Set The Sample Rate Generator (Srg) Clock
Setting the SRG Clock Divide-Down Value 7.21 Setting the SRG Clock Divide-Down Value The CLKGDV field, shown in Figure 7−24 and described in Table 7−26, contains the SRG clock divide-down value. Figure 7−24. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value SRGR1 CLKGDV...
Page 143 The maximum frequency for the McBSP on the TMS320VC5503/5507/5509 and TMS320VC5510 devices is 1/2 the CPU clock frequency. The maximum frequency for the McBSP on the TMS320VC5501 and TMS320VC5502 devices is 1/2 the frequency of the slow peripherals clock. For more...
Page 144: Register Bit Used To Set The Srg Clock Synchronization Mode
FSG pulses only in response to a pulse on the FSR pin. The frame-sync period defined in FPER is ignored. † The clock synchronization provided through the GSYNC bit is not supported on TMS320VC5501 and TMS320VC5502 devices. SPRU592E Receiver Configuration...
Page 145: Register Bits Used To Set The Srg Clock Mode (Choose An Input Clock)
Setting the SRG Clock Mode (Choosing an Input Clock) 7.23 Setting the SRG Clock Mode (Choosing an Input Clock) The bits shown in Figure 7−26 and described in Table 7−28 determine the source for the SRG clock. Not all C55x devices have a CLKS pin; check the device-specific data manual.
Page 146: Falling Edge
These bits are shown in Figure 7−27 and described in Table 7−29. Not all C55x devices have a CLKS pin; check the device-specific data manual. Note: On TMS320VC5501 and TMS320VC5502 devices, the polarity of the SRG input clock is always positive (rising edge), regardless of CLKRP or CLKXP.
Page 147 CLKS pin). The polarity determines whether the rising or falling edge of the input clock generates transitions on CLKG and FSG. Note: On TMS320VC5501 and TMS320VC5502 devices, the polarity of the SRG input clock is always positive (rising edge), regardless of CLKRP or CLKXP.
Page 148 Chapter 8 Transmitter Configuration This chapter provides details on how to configure a McBSP transmitter. Topic Page Configuring the Transmitter ........Programming McBSP Registers for Desired Transmitter Operation .
Page 149 Configuring the Transmitter 8.1 Configuring the Transmitter To configure the McBSP transmitter, perform the following procedure: 1) Place the McBSP/transmitter in reset 2) Program the McBSP registers for the desired transmitter operation 3) Take the transmitter out of reset Transmitter Configuration SPRU592E...
Page 150 Programming McBSP Registers for Desired Transmitter Operation 8.2 Programming McBSP Registers for Desired Transmitter Operation The following is a list of important tasks to be performed when you are configuring the McBSP transmitter. Each task corresponds to one or more McBSP register bit fields.
Page 151: Register Bits Used To Place Transmitter In Reset
Resetting and Enabling the Transmitter 8.3 Resetting and Enabling the Transmitter The first step of the transmitter configuration procedure is to reset the transmitter, and the last step is to enable the transmitter (to take it out of reset). Figure 8−1 and Table 8−1 describe the bits used for both of these steps. Figure 8−1.
Page 152: Reset State Of Each Mcbsp Pin
Resetting and Enabling the Transmitter 8.3.1 Reset Considerations The serial port can be reset in two ways: 1) A DSP reset (RESET signal driven low) places the receiver, transmitter, and sample rate generator in reset. When the device reset is removed (RESET signal driven high), GRST = FRST = RRST = XRST = 0, keeps the entire serial port in the reset state.
Page 153: Register Bit Used To Set Transmitter Pins To Operate As Mcbsp Pins
Setting the Transmitter Pins to Operate as McBSP Pins 8.4 Setting the Transmitter Pins to Operate as McBSP Pins Use the XIOEN bit, shown in Figure 8−2 and described in Table 8−3, to make the transmitter pins operate as McBSP pins rather than I/O pins. Figure 8−2.
Page 154 Enabling/Disabling the Digital Loopback Mode 8.5 Enabling/Disabling the Digital Loopback Mode The DLB bit determines whether the digital loopback mode is on. DLB is shown in Figure 8−3 and described in Table 8−4. Figure 8−3. Register Bit Used to Enable/Disable the Digital Loopback Mode SPCR1 R/W-0 Legend: R = Read;...
Page 155: Register Bits Used To Enable/Disable The Clock Stop Mode
Enabling/Disabling the Clock Stop Mode 8.6 Enabling/Disabling the Clock Stop Mode The CLKSTP bits determine whether the clock stop mode is on and whether a clock delay is selected. CLKSTP is shown in Figure 8−4 and described in Table 8−6. Figure 8−4.
Page 156: Register Bits Used To Enable/Disable Transmit Multichannel Selection
Enabling/Disabling Transmit Multichannel Selection 8.7 Enabling/Disabling Transmit Multichannel Selection The XMCM bits, shown in Figure 8−5 and described in Table 8−7, are used to select one of the three transmit multichannel selection modes, or to disable transmit multichannel selection. Figure 8−5. Register Bits Used to Enable/Disable Transmit Multichannel Selection MCR2 XMCM R/W-00...
Page 157: Register Bit Used To Choose One Or Two Phases For The Transmit Frame
Choosing One or Two Phases for the Transmit Frame 8.8 Choosing One or Two Phases for the Transmit Frame The XPHASE bit, shown in Figure 8−6 and described in Table 8−8, is used to choose one or two phases for the transmit frame. Figure 8−6.
Page 158: Register Bits Used To Set The Transmit Word Length(S)
Setting the Transmit Word Length(s) 8.9 Setting the Transmit Word Length(s) The XWDLEN1 an XWDLEN2 fields (see Figure 8−7 and Table 8−9) are used to set the transmit word length(s). Figure 8−7. Register Bits Used to Set the Transmit Word Length(s) XCR1 XWDLEN1 R/W-000...
Page 159 Setting the Transmit Word Length(s) 8.9.1 About the Word Length Bits Each frame can have one or two phases, depending on the value that you load into the XPHASE bit. If a single-phase frame is selected, XWDLEN1 selects the length for every serial word transmitted in the frame. If a dual-phase frame is selected, XWDLEN1 determines the length of the serial words in phase 1 of the frame, and XWDLEN2 determines the word length in phase 2 of the frame.
Page 160: Register Bits Used To Set The Transmit Frame Length
Setting the Transmit Frame Length 8.10 Setting the Transmit Frame Length The XFRLEN1 and XFRLEN2 fields (see Figure 8−8 and Table 8−10) are used to set the transmit frame length. Figure 8−8. Register Bits Used to Set the Transmit Frame Length XCR1 XFRLEN1 R/W-000 0000...
Page 161: How To Calculate Frame Length
Setting the Transmit Frame Length 8.10.1 About the Selected Frame Length The transmit frame length is the number of serial words in the transmit frame. Each frame can have one or two phases, depending on value that you load into the XPHASE bit.
Page 162: Register Bit Used To Enable/Disable The Transmit Frame-Sync Ignore Function
Enabling/Disabling the Transmit Frame-Sync Ignore Function 8.11 Enabling/Disabling the Transmit Frame-Sync Ignore Function The XFIG bit (see Figure 8−9 and Table 8−12) determines whether unexpected frame sync-pulses are ignored during transmission. Figure 8−9. Register Bit Used to Enable/Disable the Transmit Frame-Sync Ignore Function XCR2 XFIG...
Page 163: Register Bits Used To Set The Transmit Companding Mode
Setting the Transmit Companding Mode 8.12 Setting the Transmit Companding Mode The XCOMPAND field, shown in Figure 8−10 and described in Table 8−13, determine whether companding or another data transfer option is chosen for McBSP transmission. Figure 8−10. Register Bits Used to Set the Transmit Companding Mode XCR2 XCOMPAND R/W-00...
Page 164: Register Bits Used To Set The Transmit Data Delay
Setting the Transmit Data Delay 8.13 Setting the Transmit Data Delay Use the XDATDLY bits (see Figure 8−11 and Table 8−14) to select a delay of 0, 1, or 2 bits after a transmit frame-sync pulse is detected. Figure 8−11.Register Bits Used to Set the Transmit Data Delay XCR2 XDATDLY R/W-00...
Page 165: Range Of Programmable Data Delay
Setting the Transmit Data Delay Figure 8−12. Range of Programmable Data Delay CLK(R/X) FS(R/X) 0-bit delay Á D(R/X) Data delay 0 Á 1-bit delay D(R/X) Á Data delay 1 Á 2-bit delay D(R/X) Á Data delay 2 Á 8.13.2 0-Bit Data Delay Normally, a frame-sync pulse is detected or sampled with respect to an edge of serial clock internal CLK(R/X).
Page 166 Setting the Transmit Data Delay Figure 8−13. 2-Bit Data Delay Used to Skip a Framing Bit CLKR 2-bit delay Á Framing bit Á SPRU592E Transmitter Configuration 8-19...
Page 167: Register Bit Used To Set The Transmit Dxena (Dx Delay Enabler) Mode
Setting the Transmit DXENA Mode 8.14 Setting the Transmit DXENA Mode The DXENA bit (see Figure 8−14 and Table 8−15) controls the delay enabler on the DX pin. Figure 8−14. Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode SPCR1 DXENA R/W-0...
Page 168: Register Bits Used To Set The Transmit Interrupt Mode
Setting the Transmit Interrupt Mode 8.15 Setting the Transmit Interrupt Mode Use the XINTM field to select which event generates a transmit interrupt. XINTM is shown in Figure 8−16 and described in Table 8−16. Figure 8−16. Register Bits Used to Set the Transmit Interrupt Mode SPCR2 XINTM R/W-00...
Page 169: Register Bits Used To Set The Transmit Frame-Sync Mode
Setting the Transmit Frame-Sync Mode 8.16 Setting the Transmit Frame-Sync Mode The bits shown in Figure 8−17 and Table 8−17 are used to set the transmit frame-sync mode. Figure 8−17. Register Bits Used to Set the Transmit Frame-Sync Mode FSXM R/W-0 SRGR2 FSGM...
Page 170: How Fsxm And Fsgm Select The Source Of Transmit Frame-Sync Pulses
Setting the Transmit Frame-Sync Mode Table 8−18 also shows the effect of each bit setting on the FSX pin. The polarity of the signal on the FSX pin is determined by the FSXP bit. Table 8−18. How FSXM and FSGM Select the Source of Transmit Frame-Sync Pulses Source of Transmit Frame Synchronization FSXM...
Page 171: Register Bit Used To Set Transmit Frame-Sync Polarity
Setting the Transmit Frame-Sync Polarity 8.17 Setting the Transmit Frame-Sync Polarity The FSXP bit (see Figure 8−18 and Table 8−19) determines the polarity of the transmit frame-sync signal. Figure 8−18. Register Bit Used to Set Transmit Frame-Sync Polarity FSXP R/W-0 Legend: R = Read;...
Page 172 Setting the Transmit Frame-Sync Polarity FSRP, FSXP, CLKRP, and CLKXP in the pin control register (PCR) configure the polarities of the FSR, FSX, CLKR, and CLKX signals, respectively. All frame-sync signals (internal FSR, internal FSX) that are internal to the serial port are active high.
Page 173: Data Clocked Externally Using A Rising Edge And Sampled By The Mcbsp Receiver On A
Setting the Transmit Frame-Sync Polarity Figure 8−19. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge Internal CLKR Data setup Data hold Á Á Á Á 8-26 Transmitter Configuration SPRU592E...
Page 174: Register Bits Used To Set The Srg Frame-Sync Period And Pulse Width
Setting the SRG Frame-Sync Period and Pulse Width 8.18 Setting the SRG Frame-Sync Period and Pulse Width The FPER and FWID fields, shown in Figure 8−20 and described in Table 8−20, are used to set the SRG frame-sync period and pulse width. Figure 8−20.
Page 175: Frame Of Period 16 Clkg Periods And Active Width Of 2 Clkg Periods
Setting the SRG Frame-Sync Period and Pulse Width The values in FPER and FWID are loaded into separate down-counters. The 12-bit FPER counter counts down the generated clock cycles from the programmed value (4095 maximum) to 0. The 8-bit FWID counter counts down from the programmed value (255 maximum) to 0.
Page 176: Register Bit Used To Set The Transmit Clock Mode
Setting the Transmit Clock Mode 8.19 Setting the Transmit Clock Mode The CLKXM bit, shown in Figure 8−22 and described in Table 8−21, determines the source for the transmit clock and the function of the CLKX pin. Figure 8−22. Register Bit Used to Set the Transmit Clock Mode CLKXM R/W-0 Legend: R = Read;...
Page 177 Setting the Transmit Clock Mode 8.19.2 Other Considerations If the sample rate generator creates a clock signal (CLKG) that is derived from an external input clock, the GSYNC bit determines whether CLKG is kept synchronized with pulses on the FSR pin. In the clock stop mode (CLKSTP = 10b or 11b), the McBSP can act as a master or as a slave in the SPI protocol.
Page 178: Register Bit Used To Set Transmit Clock Polarity
Setting the Transmit Clock Polarity 8.20 Setting the Transmit Clock Polarity The CLKXP bit (see Figure 8−23 and Table 8−23) determines the polarity of the transmit clock. Figure 8−23. Register Bit Used to Set Transmit Clock Polarity CLKXP R/W-0 Legend: R = Read; W = Write; -n = Value after reset Table 8−23.
Page 179 Setting the Transmit Clock Polarity When FSR and FSX are outputs, implying that they are driven by the sample rate generator, they are generated (transition to their active state) on the rising edge of internal clock, CLK(R/X). Similarly, data on the DX pin is output on the rising edge of internal CLKX.
Page 180 Setting the Transmit Clock Polarity Figure 8−24. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge Internal CLKR Data setup Data hold Á Á SPRU592E Transmitter Configuration 8-33...
Page 181: Register Bits Used To Set The Sample Rate Generator (Srg) Clock
Setting the SRG Clock Divide-Down Value 8.21 Setting the SRG Clock Divide-Down Value The CLKGDV field, shown in Figure 8−25 and described in Table 8−24, is used to set the sample rate generator clock divide-down value. Figure 8−25. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value SRGR1 CLKGDV...
Page 182 The maximum frequency for the McBSP on the TMS320VC5503/5507/5509 and TMS320VC5510 devices is 1/2 the CPU clock frequency. The maximum frequency for the McBSP on the TMS320VC5501 and TMS320VC5502 devices is 1/2 the frequency of the slow peripherals clock. For more...
Page 183: Register Bit Used To Set The Srg Clock Synchronization Mode
FSG pulses only in response to a pulse on the FSR pin. The frame-sync period defined in FPER is ignored. † The clock synchronization provided through the GSYNC bit is not supported on TMS320VC5501 and TMS320VC5502 devices. 8-36 Transmitter Configuration...
Page 184: Register Bits Used To Set The Srg Clock Mode (Choose An Input Clock)
Setting the SRG Clock Mode (Choosing an Input Clock) 8.23 Setting the SRG Clock Mode (Choosing an Input Clock) The bits shown in Figure 8−27 and described in Table 8−26 are used to select the source for the SRG clock. Not all C55x devices have a CLKS pin; check the device-specific data manual.
Page 185: Register Bits Used To Set The Srg Input Clock Polarity
These bits are shown in Figure 8−28 and described in Table 8−27. Not all C55x devices have a CLKS pin; check the device-specific data manual. Note: On TMS320VC5501 and TMS320VC5502 devices, the polarity of the SRG input clock is always positive (rising edge), regardless of CLKRP or CLKXP.
Page 186: Register Bits Used To Set The Srg Input Clock Polarity
CLKS pin). The polarity determines whether the rising or falling edge of the input clock generates transitions on CLKG and FSG. Note: On TMS320VC5501 and TMS320VC5502 devices, the polarity of the SRG input clock is always positive (rising edge), regardless of CLKRP or CLKXP.
Page 187 This page is intentionally left blank. 8-40 Transmitter Configuration SPRU592E...
Page 188 Chapter 9 General-Purpose I/O on the McBSP Pins This chapter summarizes how to use the McBSP pins as general-purpose I/O (GPIO) pins. Topic Page Using the McBSP Pins for GPIO ....... .
Page 189 Using the McBSP Pins for GPIO 9.1 Using the McBSP Pins for GPIO Table 9−1 summarizes how to use the McBSP pins as general-purpose I/O (GPIO) pins. All of the bits mentioned in the table except XRST and RRST are in the pin control register.
Page 190: How To Use Mcbsp Pins For General-Purpose I/O
On the TMS320VC5503/5507/5509 and TMS320VC5510 devices, these bits are updated on every occurrence of the CPU clock. On the TMS320VC5501 and TMS320VC5502 devices, these bits are updated on every occurrence of the slow peripherals clock. SPRU592E...
Page 191 This page is intentionally left blank. General-Purpose I/O on the McBSP Pins SPRU592E...
Page 192 ........10-3 10.3 McBSP Power Management on the TMS320VC5501 and TMS320VC5502 Devices .
Page 193: Mcbsp Emulation Modes Selectable With The Free And Soft Bits Of Spcr2
Note: On the TMS320VC5501 and TMS320VC5502 devices, there is an exception to the McBSP behavior when FREE = SOFT = 0: If the McBSP is in the SPI mode, the transmitter stops immediately, but the receiver does not stop.
Page 194 McBSP Power Management on the TMS320VC5503/5507/5509 and McBSP Power Management on the TMS320VC5503/5507/5509 and TMS320VC5510 Devices 10.2 McBSP Power Management on the TMS320VC5503/5507/5509 and TMS320VC5510 Devices The McBSP is placed into its idle mode with reduced power consumption when the PERIPH idle domain is idle (PERIS = 1 in ISTR) and the McBSP idle enable bit is set (IDLEEN = 1 in PCR).
Page 195 McBSP Power Management on the TMS320VC5501 and McBSP Power Management on the TMS320VC5501 and TMS320VC5502 Devices 10.3 McBSP Power Management on the TMS320VC5501 and TMS320VC5502 Devices The McBSP is placed into its idle mode with reduced power consumption when the PERIPH idle domain is idle (PERIS = 1 in ISTR) and the McBSP idle enable bit is set (SPn = 1) in the peripheral idle control register (PICR).
Page 196: Reset State Of Each Mcbsp Pin
Resetting and Initializing a McBSP 10.4 Resetting and Initializing a McBSP 10.4.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset Table 10−2 shows the state of McBSP pins when the serial port is reset due to a DSP reset and due to a direct receiver or transmitter reset. Table 10−2.
Page 197 Resetting and Initializing a McBSP McBSP reset. When the receiver and transmitter reset bits, RRST and XRST, are loaded with 0s, the respective portions of the McBSP are reset, and activity in the corresponding section of the serial port stops. All input-only pins, such as DR and CLKS, and all other pins that are configured as inputs, are in a known state.
Page 198 Resetting and Initializing a McBSP 4) Set GRST = 1 to enable the sample rate generator. 5) Wait for two clock cycles. This ensures proper internal synchronization. 6) Set up data acquisition as required (such as writing to DXR[1,2]). 7) Make XRST = RRST = 1 to enable the serial port. Make sure that as you set these reset bits, you do not modify any of the other bits in SPCR1 and SPCR2.
Page 199 Resetting and Initializing a McBSP 10.4.4 Resetting the Transmitter While the Receiver is Running Example 10−1 shows one case in which the transmitter is reset and configured while the receiver is running. Example 10−1. Resetting and Configuring the McBSP Transmitter While the McBSP Receiver Running SPCR1 = 0001h ;...
Page 200 TMS320VC5501/02 McBSP transmitter will ignore the first frame-sync pulse after it is taken out of reset. The transmitter will transmit only on the second frame-sync pulse. The receiver will shift in data on the first frame-sync pulse regardless of whether it is generated internally or externally.
Page 201 10-10 Emulation, Power, and Reset Considerations SPRU592E...
Page 202 Chapter 11 Data Packing Examples This chapter shows two ways you can implement data packing with the McBSP. Topic Page 11.1 Data Packing Using Frame Length and Word Length ... . 11-2 11.2 Data Packing Using Word Length and the Frame-Sync Ignore Function...
Page 203: Four 8-Bit Data Words Transferred To/From The Mcbsp
Data Packing Using Frame Length and Word Length 11.1 Data Packing Using Frame Length and Word Length The frame length and word length can be manipulated to effectively pack data. For example, consider a situation where four 8-bit words are transferred in a single-phase frame as shown in Figure 11−1.
Page 204: One 32-Bit Data Word Transferred To/From The Mcbsp
Data Packing Using Frame Length and Word Length Two 16-bit data words are transferred to and from the McBSP by the CPU or by the DMA controller. Therefore, two reads, from DRR2 and DRR1, and two writes, to DXR2 and DXR1, are necessary for each frame. This results in only half the number of transfers compared to the previous case.
Page 205 Data Packing Using Word Length and the Frame-Sync Ignore Function 11.2 Data Packing Using Word Length and the Frame-Sync Ignore Function When there are multiple words per frame, you can implement data packing by increasing the word length (defining a serial word with more bits) and by ignoring frame-sync pulses.
Page 206 DXR1 to XSR1 copy Note: On the TMS320VC5501 and TMS320VC5502 devices, if a 0-bit delay and an external clock are used, the transfer shown in Figure 11−3 can only be achieved if the frame-sync ignore bit is set to 1. If the frame-sync ignore bit is 0, an additional clock cycle is required between frames.
Page 207 This page is intentionally left blank. 11-6 Data Packing Examples SPRU592E...
Page 208 Chapter 12 McBSP Registers The McBSP registers are described in this chapter. For the I/O address of each register in a particular C55x device, see the device-specific data manual. Topic Page 12.1 Data Receive Registers (DRR1 and DRR2) ..... 12-2 12.2 Data Transmit Registers (DXR1 and DXR2) .
Page 209: Data Receive Registers (Drr1 And Drr2)
Data Receive Registers (DRR1 and DRR2) 12.1 Data Receive Registers (DRR1 and DRR2) The CPU or the DMA controller reads received data from one or both of the data receive registers (see Figure 12−1). If the serial word length is 16 bits or smaller only DRR1 is used.
Page 210: Data Transmit Registers (Dxr1 And Dxr2)
Data Transmit Registers (DXR1 and DXR2) 12.2 Data Transmit Registers (DXR1 and DXR2) For transmission, the CPU or the DMA controller writes data to one or both of the data transmit registers (see Figure 12−2). If the serial word length is 16 bits or smaller, only DXR1 is used.
Page 211 Serial Port Control Registers (SPCR1 and SPCR2) 12.3 Serial Port Control Registers (SPCR1 and SPCR2) Each McBSP has two serial port control registers of the form shown in Figure 12−3. Table 12−1 and Table 12−2 describe the bits in SPCR1 and SPCR2, respectively.
Page 212: Spcr1 Bit Descriptions
Serial Port Control Registers (SPCR1 and SPCR2) Table 12−1. SPCR1 Bit Descriptions Field Value Description Digital loopback mode bit. DLB disables or enables the digital loopback mode of the McBSP: Disabled Internal DR is supplied by the DR pin. Internal FSR and internal CLKR can be supplied by their respective pins or by the sample rate generator, depending on the mode bits FSRM and CLKRM.
Page 213 Serial Port Control Registers (SPCR1 and SPCR2) Table 12−1. SPCR1 Bit Descriptions (Continued) Field Value Description 12–11 CLKSTP Clock stop mode bits. CLKSTP allows you to use the clock stop mode to support the SPI master-slave protocol. If you will not be using the SPI protocol, you can clear CLKSTP to disable the clock stop mode.
Page 214 Serial Port Control Registers (SPCR1 and SPCR2) Table 12−1. SPCR1 Bit Descriptions (Continued) Field Value Description 5–4 RINTM Receive interrupt mode bits. RINTM determines which event in the McBSP receiver generates a receive interrupt (RINT) request. If RINT is properly enabled inside the CPU, the CPU services the interrupt request;...
Page 215 Serial Port Control Registers (SPCR1 and SPCR2) Table 12−1. SPCR1 Bit Descriptions (Continued) Field Value Description RRDY Receiver ready bit. RRDY is set when data is ready to be read from DRR[1,2]. Specifically, RRDY is set in response to a copy from RBR1 to DRR1.
Page 216: Spcr2 Bit Descriptions
Soft stop. The McBSP transmit clock stops after completion of the current serial word transfer. The McBSP receive clock is not affected. On the TMS320VC5501 and TMS320VC5502 devices, the SOFT operation works as described above. On the TMS320VC5510 and TMS320VC5503/5507/5509 devices, support for SOFT=1 is not available.
Page 217 Serial Port Control Registers (SPCR1 and SPCR2) Table 12−2. SPCR2 Bit Descriptions (Continued) Field Value Description FRST Frame-sync logic reset bit. The sample rate generator of the McBSP includes frame-sync logic to generate an internal frame-sync signal. You can use FRST to take the frame-sync logic into and out of its reset state. Note: This bit has a negative polarity;...
Page 218 Serial Port Control Registers (SPCR1 and SPCR2) Table 12−2. SPCR2 Bit Descriptions (Continued) Field Value Description 5–4 XINTM Transmit interrupt mode bits. XINTM determines which event in the McBSP transmitter generates a transmit interrupt (XINT) request. If XINT is properly enabled, the CPU services the interrupt request;...
Page 219 Serial Port Control Registers (SPCR1 and SPCR2) Table 12−2. SPCR2 Bit Descriptions (Continued) Field Value Description XEMPTY Transmitter empty bit. XEMPTY is cleared when the transmitter is ready to send new data but no new data is available (transmitter-empty condition). Note: This bit has a negative polarity;...
Page 220: Receive Control Registers (Rcr1 And Rcr2)
Receive Control Registers (RCR1 and RCR2) 12.4 Receive Control Registers (RCR1 and RCR2) Each McBSP has two receive control registers of the form shown in Figure 12−4. Table 12−3 and Table 12−4 describe the bits of RCR1 and RCR2, respectively. These I/O-mapped registers enable you to: Specify one or two phases for each frame of receive data (RPHASE) Define two parameters for phase 1 and (if necessary) phase 2: the serial word length (RWDLEN1, RWDLEN2) and the number of words...
Page 221: Rcr1 Bit Descriptions
Receive Control Registers (RCR1 and RCR2) Table 12−3. RCR1 BIt Descriptions Field Value Description Reserved Reserved bits (not available for your use). They are read-only bits and return 0s when read. 14–8 RFRLEN1 0-127 Receive frame length 1 bits (1 to 128 words). Each frame of receive data can have one or two phases, depending on value that you load into the RPHASE bit.
Page 222 Receive Control Registers (RCR1 and RCR2) Table 12−3. RCR1 BIt Descriptions (Continued) Field Value Description 7–5 RWDLEN1 Receive word length 1 bits. Each frame of receive data can have one or two phases, depending on the value that you load into the RPHASE bit. If a single-phase frame is selected, RWDLEN1 in RCR1 selects the length for every serial word received in the frame.
Page 223: Rcr2 Bit Descriptions
Receive Control Registers (RCR1 and RCR2) Table 12−4. RCR2 Bit Descriptions Field Value Description RPHASE Receive phase number bit. RPHASE determines whether the receive frame has one phase or two phases. For each phase you can define the serial word length and the number of serial words in the phase. To set up phase 1, program RWDLEN1 (word length) and RFRLEN1 (number of words).
Page 224 Receive Control Registers (RCR1 and RCR2) Table 12−4. RCR2 BIt Descriptions (Continued) Field Value Description 7–5 RWDLEN2 Receive word length 2 bits. Each frame of receive data can have one or two phases, depending on the value that you load into the RPHASE bit. If a single-phase frame is selected, RWDLEN1 in RCR1 selects the length for every serial word received in the frame.
Page 225 Receive Control Registers (RCR1 and RCR2) Table 12−4. RCR2 BIt Descriptions (Continued) Field Value Description RFIG Receive frame-sync ignore bit. If a frame-sync pulse starts the transfer of a new frame before the current frame is fully received, this pulse is treated as an unexpected frame-sync pulse.
Page 226: Transmit Control Registers (Xcr1 And Xcr2)
Transmit Control Registers (XCR1 and XCR2) 12.5 Transmit Control Registers (XCR1 and XCR2) Each McBSP has two transmit control registers of the form shown in Figure 12−5. Table 12−5 and Table 12−6 describe the bits of XCR1 and XCR2, respectively. These I/O-mapped registers enable you to: Specify one or two phases for each frame of transmit data (XPHASE) Define two parameters for phase 1 and (if necessary) phase 2: the serial word length (XWDLEN1, XWDLEN2) and the number of words...
Page 227: Xcr1 Bit Descriptions
Transmit Control Registers (XCR1 and XCR2) Table 12−5. XCR1 Bit Descriptions Field Value Description Reserved Reserved bits (not available for your use). They are read-only bits and return 0s when read. 14–8 XFRLEN1 0-127 Transmit frame length 1 (1 to 128 words). Each frame of transmit data can have one or two phases, depending on value that you load into the XPHASE bit.
Page 228 Transmit Control Registers (XCR1 and XCR2) Table 12−5. XCR1 Bit Descriptions (Continued) Field Value Description 7–5 XWDLEN1 Transmit word length 1. Each frame of transmit data can have one or two phases, depending on the value that you load into the XPHASE bit. If a single-phase frame is selected, XWDLEN1 in XCR1 selects the length for every serial word transmitted in the frame.
Page 229: Xcr2 Bit Descriptions
Transmit Control Registers (XCR1 and XCR2) Table 12−6. XCR2 Bit Descriptions Field Value Description XPHASE Transmit phase number bit. XPHASE determines whether the transmit frame has one phase or two phases. For each phase you can define the serial word length and the number of serial words in the phase. To set up phase 1, program XWDLEN1 (word length) and XFRLEN1 (number of words).
Page 230 Transmit Control Registers (XCR1 and XCR2) Table 12−6. XCR2 Bit Descriptions (Continued) Field Value Description 7–5 XWDLEN2 Transmit word length 2. Each frame of transmit data can have one or two phases, depending on the value that you load into the XPHASE bit. If a single-phase frame is selected, XWDLEN1 in XCR1 selects the length for every serial word transmitted in the frame.
Page 231 Transmit Control Registers (XCR1 and XCR2) Table 12−6. XCR2 Bit Descriptions (Continued) Field Value Description XFIG Transmit frame-sync ignore bit. If a frame-sync pulse starts the transfer of a new frame before the current frame is fully transmitted, this pulse is treated as an unexpected frame-sync pulse.
Page 232: Sample Rate Generator Registers (Srgr1 And Srgr2)
Notes: 1) Not all C55x devices have a CLKS pin; check the device-specific data manual. 2) On TMS320VC5501 and TMS320VC5502 devices, the polarity of the SRG input clock is always positive (rising edge), regardless of CLKRP or CLKXP. 3) The clock synchronization provided through the GSYNC bit is not supported on TMS320VC5501 and TMS320VC5502 devices.
Page 233: Srgr1 Bit Descriptions
Sample Rate Generator Registers (SRGR1 and SRGR2) Figure 12−6. Sample Rate Generator Registers (SRGR1 and SRGR2) SRGR1 FWID R/W-0 CLKGDV R/W-1 SRGR2 † ‡ GSYNC CLKSP CLKSM FSGM FPER R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 FPER R/W-0 Legend: R = Read; W = Write; -n = Value after reset †...
Page 234: Divide-Down Value
TMS320VC5503/5507/5509 and TMS320VC5510 devices is 1/2 the CPU clock frequency. The maximum frequency for the McBSP on the TMS320VC5501 and TMS320VC5502 devices is 1/2 the frequency of the slow peripherals clock. See the device-specific data manual for timing requirements for the McBSP.
Page 235: Srgr2 Bit Descriptions
(FSG) generated by the sample rate generator are made dependent on pulses on the FSR pin. On TMS320VC5501 and TMS320VC5502 devices: The GSYNC function not available, and this is a reserved bit. Always write 0 to this bit.
Page 236 Sample Rate Generator Registers (SRGR1 and SRGR2) Table 12−8. SRGR2 Bit Descriptions (Continued) Field Value Description Description CLKSM Sample rate generator input clock mode bit. The sample rate generator can accept an input clock signal and divide it down according to CLKGDV to produce an output clock signal, CLKG.
Page 237 Sample Rate Generator Registers (SRGR1 and SRGR2) Table 12−8. SRGR2 Bit Descriptions (Continued) Field Value Description Description FSGM Sample rate generator transmit frame-sync mode bit. The transmitter can get frame synchronization from the FSX pin (FSXM = 0) or from inside the McBSP (FSXM = 1).
Page 238: Multichannel Control Registers (Mcr1 And Mcr2)
Multichannel Control Registers (MCR1 and MCR2) 12.7 Multichannel Control Registers (MCR1 and MCR2) Each McBSP has two multichannel control registers of the form shown in Figure 12−7. MCR1 has control and status bits (with an R prefix) for multichannel selection operation in the receiver. MCR2 contains the same type of bits (bit with an X prefix) for the transmitter.
Page 239: Mcr1 Bit Descriptions
Multichannel Control Registers (MCR1 and MCR2) Table 12−9. MCR1 Bit Descriptions Field Value Description 15-10 Reserved Reserved bits (not available for your use). They are read-only bits and return 0s when read. RMCME Receive multichannel partition mode bit. RMCME is only applicable if channels can be individually enabled or disabled for reception (RMCM = 1).
Page 240 Multichannel Control Registers (MCR1 and MCR2) Table 12−9. MCR1 Bit Descriptions (Continued) Field Value Description 8–7 RPBBLK Receive partition B block bits RPBBLK is only applicable if channels can be individually enabled or disabled (RMCM = 1) and the 2-partition mode is selected (RMCME = 0). Under these conditions, the McBSP receiver can accept or ignore data in any of the 32 channels that are assigned to partitions A and B of the receiver.
Page 241 Multichannel Control Registers (MCR1 and MCR2) Table 12−9. MCR1 Bit Descriptions (Continued) Field Value Description 4–2 RCBLK Receive current block indicator. RCBLK indicates which block of 16 channels is involved in the current McBSP reception: 000b Block 0: channels 0 through 15 001b Block 1: channels 16 through 31 010b...
Page 242 Multichannel Control Registers (MCR1 and MCR2) Table 12−10. MCR2 Bit Descriptions Field Value Description 15-10 Reserved Reserved bits (not available for your use). They are read-only bits and return 0s when read. XMCME Transmit multichannel partition mode bit. XMCME determines whether only 32 channels or all 128 channels are to be individually selectable.
Page 243 Multichannel Control Registers (MCR1 and MCR2) Table 12−10. MCR2 Bit Descriptions (Continued) Field Value Description 8–7 XPBBLK Transmit partition B block bits XPBBLK is only applicable if channels can be individually disabled/enabled and masked/unmasked (XMCM is nonzero) and the 2-partition mode is selected (XMCME = 0).
Page 244 Multichannel Control Registers (MCR1 and MCR2) Table 12−10. MCR2 Bit Descriptions (Continued) Field Value Description 4–2 XCBLK Transmit current block indicator. XCBLK indicates which block of 16 channels is involved in the current McBSP transmission: 000b Block 0: channels 0 through 15 001b Block 1: channels 16 through 31 010b...
Page 245: Pin Control Register (Pcr)
(IDLEEN, in conjunction with the PERI bit of ICR). For the TMS320VC5503/5507/5509 and TMS320VC5510 devices, this capability is provided in the PCR. On the TMS320VC5501 and TMS320VC5502 devices, this capability is provided in the Peripheral Idle Control Register (PICR). For more information on the TMS320VC5501 implementation, see the TMS320VC5501 Fixed-Point Digital Signal Processor Data Manual (literature number SPRS206);...
Page 246 Reserved IDLEEN = 1, the McBSP stops and enters a low-power state. On the TMS320VC5501 and TMS320VC5502 devices: This bit is reserved and should be written as 0. The IDLEEN function is implemented in the Peripheral Idle Control Register (PICR). For more information on the PICR,...
Page 247 Pin Control Register (PCR) Table 12−11. PCR Bit Descriptions (Continued) Field Value Description RIOEN Receive I/O enable bit. When the receiver is in reset (RRST = 0), RIOEN can configure certain McBSP pins as general-purpose I/O (GPIO) pins . For a summary, see the table that follows the RIOEN bit description.
Page 248 Pin Control Register (PCR) Table 12−11.PCR Bit Descriptions (Continued) Field Value Description FSXM Transmit frame-sync mode bit. FSXM determines whether transmit frame-sync pulses are supplied externally or internally. The polarity of the signal on the FSX pin is determined by the FSXP bit. Transmit frame synchronization is supplied by an external source via the FSX pin.
Page 249 Pin Control Register (PCR) Table 12−11.PCR Bit Descriptions (Continued) Field Value Description CLKXM Transmit clock mode bit. CLKXM determines whether the source for the transmit clock is external or internal, and whether the CLKX pin is an input or an output. The polarity of the signal on the CLKX pin is determined by the CLKXP bit.
Page 250 Pin Control Register (PCR) Table 12−11.PCR Bit Descriptions (Continued) Field Value Description CLKRM Receive clock mode bit. The role of CLKRM and the resulting effect on the CLKR pin depend on whether the McBSP is in the digital loopback mode (DLB = 1).
Page 251 Pin Control Register (PCR) Table 12−11.PCR Bit Descriptions (Continued) Field Value Description SCLKME Sample rate generator input clock mode bit. The sample rate generator can produce a clock signal, CLKG. The frequency of CLKG is: CLKG freq. = (Input clock frequency) / (CLKGDV + 1) SCLKME is used in conjunction with the CLKSM bit to select the input clock.
Page 252 Pin Control Register (PCR) Table 12−11.PCR Bit Descriptions (Continued) Field Value Description DRSTAT DR pin status bit. When DRSTAT is applicable, it reflects the level on the DR pin. DRSTAT is only applicable when the receiver is in reset (RRST = 0) and DR is configured for use as a general-purpose input pin (RIOEN = 1).
Page 253: Format Of The Receive Channel Enable Registers (Rcera-Rcerh)
Receive Channel Enable Registers (RCERA-RCERH) 12.9 Receive Channel Enable Registers (RCERA-RCERH) Each McBSP has eight receive channel enable registers of the format shown in Figure 12−9. There is one for each of the receive partitions: A, B, C, D, E, F, G, and H.
Page 254 Receive Channel Enable Registers (RCERA-RCERH) 12.9.1 RCERs Used in the Receive Multichannel Selection Mode For multichannel selection operation, the assignment of channels to the RCERs depends on whether 32 or 128 channels are individually selectable, as defined by the RMCME bit. For each of these two cases, Table 12−13 shows which block of channels is assigned to each of the RCERs used.
Page 255 Receive Channel Enable Registers (RCERA-RCERH) Table 12−13. Use of the Receive Channel Enable Registers (Continued) Number of Number of Block Assignments Channel Assignments Selectable Selectable RCERx Block Assigned Bit in RCERx Channel Assigned Channels Channels RCERE Block 4 RCE0 Channel 64 RCE1 Channel 65 RCE2...
Page 256 Transmit Channel Enable Registers (XCERA-XCERH) 12.10 Transmit Channel Enable Registers (XCERA-XCERH) Each McBSP has eight transmit channel enable registers of the form shown in Figure 12−10. There is one for each of the transmit partitions: A, B, C, D, E, F, G, and H.
Page 257 Transmit Channel Enable Registers (XCERA-XCERH) Table 12−14. Description For Bit x of a Transmit Channel Enable Register (x = 0, 1, 2, ..., or 15) Field Value Description XCEx Transmit channel enable bit. The role of this bit depends on which transmit multichannel selection mode is selected with the XMCM bits.
Page 258 Transmit Channel Enable Registers (XCERA-XCERH) Table 12−15. Use of the Transmit Channel Enable Registers in a Transmit Multichannel Selection Mode Number of Block Assignments Channel Assignments Selectable t bl XCERx Block Assigned Bit in XCERx Channel Assigned Channels XCERA Channels n to (n + 15) XCE0 Channel n (XMCME = 0)
Page 259 Transmit Channel Enable Registers (XCERA-XCERH) Table 12−15. Use of the Transmit Channel Enable Registers in a Transmit Multichannel Selection Mode (Continued) Number of Number of Block Assignments Channel Assignments Selectable Selectable XCERx Block Assigned Bit in XCERx Channel Assigned Channels Channels XCERE Block 4...
Page 260 Chapter 13 McBSP Register Worksheet This register worksheet is meant to be printed and used as a guide for configuring the McBSP registers. Each figure on the worksheet provides space in every register field for entering the binary value that needs to be loaded into that field.
Page 261 General Control Registers 13.1 General Control Registers Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á SPCR1 − Initialization Value: ___________________________________________________________ Á...
Page 262 Á Á † On the TMS320VC5501 and TMS320VC5502 devices, this bit is reserved and should be written with 0. Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 263 Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á † On TMS320VC5501 and TMS320VC5502 devices, this bit is reserved and should be written with 0. 13-4 McBSP Register Worksheet SPRU592E...
Page 264 Multichannel Selection Control Registers 13.2 Multichannel Selection Control Registers Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á MCR1 −...
Page 265 Multichannel Selection Control Registers RCERB − Initialization Value: ___________________________________________________________ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 266 Multichannel Selection Control Registers RCERD − Initialization Value: ___________________________________________________________ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 267 Multichannel Selection Control Registers RCERF − Initialization Value: ___________________________________________________________ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 268 Multichannel Selection Control Registers RCERH − Initialization Value: ___________________________________________________________ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 269 Multichannel Selection Control Registers XCERB − Initialization Value: ___________________________________________________________ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 270 Multichannel Selection Control Registers XCERD − Initialization Value: ___________________________________________________________ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 271 Multichannel Selection Control Registers XCERF − Initialization Value: ___________________________________________________________ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 272 Multichannel Selection Control Registers XCERH − Initialization Value: ___________________________________________________________ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
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Page 274: Document Revision History
Appendix A Appendix A Revision History Table A−1 lists the changes made since the previous version of the document. Table A−1. Document Revision History Page Additions/Modifications/Deletions 2-10 Changed the second note on page 2-10. 2-14 Changed the note on page 2-14. 11-5 Changed the note on page 11-5.
Page 275 Index Index µ-law format (companding) 2-4 CLKRP bit of PCR described in table 12-45 shown in figure 12-39 CLKS pin 1-6 CLKS pin polarity bit (CLKSP) A-law format (companding) 2-4 described in table 12-28 AC97 standard implemented in McBSP 2-13 shown in figure 12-26 CLKS pin status bit (CLKSSTAT) described in table 12-44...
Page 276 Index clock mode data packing in McBSP receiver 7-31 using frame length and word length 11-2 sample rate generator using word length and the frame-sync ignore receiver configuration 7-40 function 11-4 transmitter configuration 8-37 data receive registers (DRR1 and DRR2) 12-2 transmitter 8-29 data reception in McBSP 2-15 clock polarity...
Page 277 Index DX pin status bit (DXSTAT) frame-sync logic reset bit (FRST) described in table 12-44 described in table 12-10 shown in figure 12-39 shown in figure 12-4 DXENA bit of SPCR1 frame-sync mode described in table 12-6 receiver configuration 7-23 shown in figure 12-4 transmitter configuration 8-22 DXR1 and DXR2 12-3...
Page 278 McBSP data transfer process 2-2 McBSP internal input clock, shown in McBSP diagram 1-4 idle modes of McBSP McBSP introduction 1-1 TMS320VC5501 and TMS320VC5502 McBSP operation 2-1 devices 10-4 TMS320VC5503/5507/5509 and McBSP receive multichannel selection mode 7-9 TMS320VC5510 devices 10-3...
Page 279 12-13 pulses 4-11 receive DMA event signal (REVT) 2-19 power reduction from idling McBSP receive frame length 7-13 TMS320VC5501 and TMS320VC5502 receive frame length 1 bits (RFRLEN1) devices 10-4 described in table 12-14 TMS320VC5503/5507/5509 and shown in figure 12-13...
Page 280 (RMCME) register worksheet for McBSP 13-1 described in table 12-32 registers of McBSP 12-1 shown in figure 12-31 related documentation from Texas Instruments iii receive multichannel selection mode resetting McBSP 10-5 enabling/disabling 7-9 introduced 5-10...
Page 281 Index RFULL bit of SPCR1 described in table 12-7 shown in figure 12-4 sample rate generator 3-2 RINT signal 2-19 clock divide-down value RINTM bits of SPCR1 receiver configuration 7-37 described in table 12-7 transmitter configuration 8-34 shown in figure 12-4 clock mode (input clock selection) receiver configuration 7-40 RIOEN bit of PCR...
Page 282 Index serial port control registers (SPCR1 and transmit data delay bits (XDATDLY) SPCR2) 12-4 described in table 12-24 shown in figure 12-19 serial word 2-7 transmit DMA event signal (XEVT) 2-19 serial word length(s) receiver configuration 7-11 transmit DX delay enabler mode 8-20 transmitter configuration 8-11 transmit frame length 8-13 sign-extension of receive data 7-20...
Page 283 Index transmit partition A block bits (XPABLK) described in table 12-36 shown in figure 12-31 XCBLK bits of MCR2 transmit partition B block bits (XPBBLK) described in table 12-37 described in table 12-36 shown in figure 12-31 shown in figure 12-31 XCE0-XCE15 bits of an XCER transmit phase number bit (XPHASE) described in table 12-50...
Page 284 Index XPHASE bit of XCR2 XSYNCERR bit of SPCR2 described in table 12-22 described in table 12-11 shown in figure 12-19 shown in figure 12-4 XRDY bit of SPCR2 XWDLEN1 bits of XCR1 described in table 12-12 described in table 12-21 shown in figure 12-4 shown in figure 12-19 XRST bit of SPCR2...
Page 285 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

This manual is also suitable for:

Tms320vc5502 Tms320vc5503 Tms320vc5507 Tms320vc5509 Tms320vc5510

Texas Instruments TMS320VC5501 Reference Manual

Table of Contents

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Chapter 3 Sample Rate Generator of the Mcbsp

Chapter 4 Mcbsp Exception/Error Conditions

Chapter 5 Multichannel Selection Modes

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