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2.4.2 Video Port Status Register (VPSTAT)
The video port status register (VPSTAT) indicates the current condition of the video port.
The video port status register (VPSTAT) is shown in
31
15
LEGEND: R = Read only; -n = value after reset
Table 2-4. Video Port Status Register (VPSTAT) Field Descriptions
(1)
Bit
field
symval
31-4
Reserved
-
3
DCDIS
OF(value)
DEFAULT
ENABLE
DISABLE
2
HIDATA
OF(value)
DEFAULT
NONE
USE
1-0
Reserved
-
(1)
For CSL implementation, use the notation VP_VPSTAT_field_symval
SPRUEM1 – May 2007
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Figure 2-2. Video Port Status Register (VPSTAT)
Reserved
Reserved
R-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
Dual-channel disable bit. The default value is determined by the chip-level
configuration.
0
Dual-channel operation is enabled.
1
Port muxing selections prevent dual-channel operation.
High data bus half. HIDATA does not affect video port operation but is provided to
inform you which VDATA pins may be controlled by the video port GPIO registers.
HIDATA is never set unless DCDIS is also set. The default value is determined by the
chip-level configuration.
0
1
Indicates that another peripheral is using VDATA[9-2] and the video port channel A
(VDIN[9-2] or VDOUT[9-2]) is muxed onto VDATA[19-12].
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
Figure 2-2
and described in
R-0
4
Video Port Control Registers
Table
2-4.
3
2
1
DCDIS
HIDATA
Reserved
R-x
R-x
R-0
Video Port
16
0
37
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