Video Display Field 2 Timing Register (Vdfldt2); Video Display Field 1 Timing Register (Vdfldt1); Video Display Field 1 Timing Register (Vdfldt1) Field Descriptions; Video Display Field 2 Timing Register (Vdfldt2) Field Descriptions - Texas Instruments TMS320DM648 User Manual

Video Display Registers
31 28
Reserved
R-0
15 12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-18. Video Display Field 1 Timing Register (VDFLDT1) Field Descriptions
(1)
Bit field symval
31-28 Reserved -
27-16 FLD1YSTART OF(value)
DEFAULT
15-12 Reserved -
11-0 FLD1XSTART OF(value)
DEFAULT
(1)
For CSL implementation, use the notation VP_VDFLDT1_field_symval

4.12.14 Video Display Field 2 Timing Register (VDFLDT2)

The video display field 2 timing register (VDFLDT2) sets the timing of the field identification signal.
In raw data mode, the FLD signal is asserted whenever the frame line counter (FLCOUNT) is equal to
FLD2YSTART and the frame pixel counter (FPCOUNT) is equal to FLD2XSTART (this is shown in
Figure 4-6.
In BT.656 and Y/C mode, the FLD signal is asserted to indicate field 2 display whenever FLCOUNT =
FLD2YSTART and FPCOUNT = FLD2XSTART. The FLD output is completely independent of the timing
control codes. The F bit in the EAV/SAV codes is controlled by the VDFBIT register.
The video display field 2 timing register (VDFLDT2) is shown in
31 28
Reserved
R-0
15 12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-19. Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions
(1)
Bit field symval
31-28 Reserved -
27-16 FLD2YSTART OF(value)
DEFAULT
15-12 Reserved -
(1)
For CSL implementation, use the notation VP_VDFLDT2_field_symval
136 Video Display Port
Figure 4-43. Video Display Field 1 Timing Register (VDFLDT1)
27
11
(1)
Value Description
0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
0-FFFh Specifies the first line of field 1. (The line where FLD is asserted.)
0
0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
0-FFFh Specifies the pixel on the first line of field 1 where the FLD output is asserted.
0
Figure 4-44. Video Display Field 2 Timing Register (VDFLDT2)
27
11
(1)
Value Description
0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
0-FFFh Specifies the first line of field 2. (The line where FLD is asserted.)
0
0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
FLD1YSTART
R/W-0
FLD1XSTART
R/W-0
Figure 4-44 and described in
FLD2YSTART
R/W-0
FLD2XSTART
R/W-0
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16
0
Table 4-19.
16
0
SPRUEM1 – May 2007