Texas Instruments TMS320 User Manual
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Texas Instruments TMS320 User Manual

Second generation digital signal processors
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80-ns Instruction Cycle Time
544 Words of On-Chip Data RAM
4K Words of On-Chip Secure Program
EPROM (TMS320E25)
4K Words of On-Chip Program ROM
(TMS320C25)
128K Words of Data/Program Space
32-Bit ALU/Accumulator
16  16-Bit Multiplier With a 32-Bit Product
Block Moves for Data/Program
Management
Repeat Instructions for Efficient Use of
Program Space
Serial Port for Direct Codec Interface
Synchronization Input for Synchronous
Multiprocessor Configurations
Wait States for Communication to Slow
Off-Chip Memories/Peripherals
On-Chip Timer for Control Operations
Single 5-V Supply
Packaging: 68-Pin PGA, PLCC, and
CER-QUAD
68-to-28 Pin Conversion Adapter Socket for
EPROM Programming
Commercial and Military Versions Available
NMOS Technology:
— TMS32020
. . . . . . . . .
CMOS Technology:
— TMS320C25
. . . . . . . .
— TMS320E25
. . . . . . . .
— TMS320C25-50
description
This data sheet provides complete design documentation for the second-generation devices of the TMS320
family. This facilitates the selection of the devices best suited for user applications by providing all specifications
and special features for each TMS320 member. This data sheet is divided into four major sections: architecture,
electrical specifications (NMOS and CMOS), timing diagrams, and mechanical data. In each of these sections,
generic information is presented first, followed by specific device information. An index is provided for quick
reference to specific information about a device.
ADVANCE INFORMATION concerns new products in the
sampling or preproduction phase of development.
Characteristic data and other specifications are subject to
change without notice.
200-ns cycle time
100-ns cycle time
100-ns cycle time
. . . . . .
80-ns cycle time
POST OFFICE BOX 1443
TMS320 SECOND GENERATION
DIGITAL SIGNAL PROCESSORS
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990
68-Pin GB Package
(Top View)
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
68-Pin FN and FZ Packages
(Top View)
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
V
10
SS
D7
11
D6
12
D5
13
D4
14
D3
15
D2
16
D1
17
D0
18
SYNC
19
INT0
20
INT1
21
INT2
22
V
23
CC
DR
24
FSR
25
A0
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Copyright
HOUSTON, TEXAS 77001
†
†
IACK
60
MSC
59
CLKOUT1
58
CLKOUT2
57
XF
56
HOLDA
55
DX
54
FSX
53
X2 CLKIN
52
X1
51
BR
50
49
STRB
48
R/W
47
PS
46
IS
45
DS
44
V
SS
1991, Texas Instruments Incorporated
1

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Summary of Contents for Texas Instruments TMS320

  • Page 1 This facilitates the selection of the devices best suited for user applications by providing all specifications and special features for each TMS320 member. This data sheet is divided into four major sections: architecture, electrical specifications (NMOS and CMOS), timing diagrams, and mechanical data. In each of these sections, generic information is presented first, followed by specific device information.
  • Page 2 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION K1/26 K8/40 E1/16 A5/3 INT2 H1/22 H2/23 K2/28 L9/41 D2/15 B6/2 J11/46 L6/35 † L3/29...
  • Page 3 The TMS32010, the first NMOS digital signal processor in the TMS320 family, was introduced in 1983. Its powerful instruction set, inherent flexibility, high-speed number-crunching capabilities, and innovative architecture have made this high-performance, cost-effective processor the ideal solution to many telecommunications, computer, commercial, industrial, and military applications.
  • Page 4 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Key Features: TMS32020 +5 V  200-ns Instruction Cycle Time  544 Words of On-Chip Data RAM  Interrupts 256-Word 288-Word 128K Words of Total Data/Program...
  • Page 5 Military version planned; contact nearest TI Field Sales Office for details. architecture The TMS320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and execution.
  • Page 6 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 functional block diagram (TMS320C2x) SYNC Program Bus PFC(16) QIR(16) IR(16) STRB READY STO(16) ST1(16) RPTC(8) HOLD HOLDA IFR(6) MCS(16) PC(16) CLKR IACK CLKX Address Stack MP/MC...
  • Page 7 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 scaling shifter The TMS320C2x scaling shifter has 16-bit input connected to the data bus and a 32-bit output connected to the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction.
  • Page 8 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Program Program Data 0(0000h) 0(0000h) 0(0000h) Interrupts Interrupts On-Chip and Reserved and Reserved Memory-Mapped (On-Chip (External) Registers ROM/EPROM) 31(001Fh) 5(0005h) 31(001Fh) 32(0020h ) 6(0006h) 32(0020h )
  • Page 9 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 interrupts and subroutines The TMS320C2x has three external maskable user interrupts INT2-INT0, available for external devices that interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software interrupt (TRAP) instruction.

  • Page 10: Instruction Set

    TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 instruction set The TMS320C2x microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal processing operations as well as general-purpose applications, such as multiprocessing and high-speed control. The TMS32020 source code is upward-compatible with TMS320C25 source code.

  • Page 11: Instruction Set Summary

    TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 instruction set summary Table 2 lists the symbols and abbreviations used in Table 3, the TMS320C25 instruction set summary. Table 3 consists primarily of single-cycle, single-word instructions. Infrequently used branch, I/O, and CALL instructions are multicycle.
  • Page 12 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 3. TMS320C25 Instruction Set Summary ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS INSTRUCTION BIT CODE MNEMONIC DESCRIPTION WORDS Absolute value of accumulator Add to accumulator with shift ‡...
  • Page 13 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 3. TMS320C25 Instruction Set Summary (continued) ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS INSTRUCTION BIT CODE MNEMONIC DESCRIPTION WORDS Subtract from accumulator with shift specified by † SUBT...
  • Page 14 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 3. TMS320C25 Instruction Set Summary (continued) T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS INSTRUCTION BIT CODE MNEMONIC DESCRIPTION WORDS APAC Add P register to accumulator †...
  • Page 15 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 3. TMS320C25 Instruction Set Summary (continued) BRANCH/CALL INSTRUCTIONS INSTRUCTION BIT CODE MNEMONIC DESCRIPTION WORDS Branch unconditionally † BACC Branch to address specified by accumulator BANZ Branch on auxiliary register not zero †...
  • Page 16 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 3. TMS320C25 Instruction Set Summary (concluded) CONTROL INSTRUCTIONS INSTRUCTION BIT CODE MNEMONIC DESCRIPTION WORDS † Test bit † BITT Test bit specified by T register †...
  • Page 17 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 TMS32020 PRODUCT NOTIFICATION Texas Instruments has identified an unusual set of circumstances that will cause the BIT (Test Bit) instruction on the TMS32020 to affect the contents of the accumulator; ideally, the BIT instruction should not affect the accumulator.

  • Page 18: Development Support

    System development may begin with the use of the simulator, Software Development System (SWDS), or emulator (XDS) along with an assembler/linker. These tools give the TMS320 user various means of evaluation, from software simulation of the second-generation TMS320s (simulator) to full-speed in-circuit emulation with hardware and software breakpoint trace and timing capabilities (XDS).
  • Page 19 XDS/22 Upgrade (TMS32020 to TMS320C2x) TMDX3282226 NOTE: Emulation support for the TMS320C25-50 is available from Macrochip Research, Inc.; refer to the TMS320 Family Development Support Reference Guide (SPRU011A) for the mailing address. IBM is a trademark of International Business Machines Corporation.

  • Page 20: Documentation Support

    The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board service provides access to large amounts of information pertaining to the TMS320 family.

  • Page 21: Recommended Operating Conditions

    In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. ...
  • Page 22 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 CLOCK CHARACTERISTICS AND TIMING The TMS32020 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency is one-fourth the crystal fundamental frequency.
  • Page 23 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 timing requirements over recommended operating conditions (see Note 3) UNIT CLKIN cycle time c(C) † CLKIN fall time f(CI) † CLKIN rise time r(CI) CLKIN low pulse duration, t...
  • Page 24 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER UNIT STRB from CLKOUT1 (if STRB is present) Q -- 15...

  • Page 25: Hold Timing

    TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 RS, INT, BIO, AND XF TIMING switching characteristics over recommended operating conditions (see Note 3 and 8) PARAMETER UNIT CLKOUT1 low to reset state entered d(RS)
  • Page 26 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER UNIT DX valid after CLKX rising edge (see Note 10) d(CH-DX) DX valid after FSX falling edge (TXM = 0, see Note 10)
  • Page 27 In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either V or ground. Specific guidelines for handling devices of this type are contained in the publication “Guidelines for Handling Electrostatic-Discharge Sensitive (ESDS) Devices and Assemblies” available from Texas Instruments  POST OFFICE BOX 1443...
  • Page 28 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 CLOCK CHARACTERISTICS AND TIMING The TMS32025 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency is one-fourth the crystal fundamental frequency.
  • Page 29 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 timing requirements over recommended operating conditions (see Note 3) UNIT CLKIN cycle time 24.4 c(CI) † CLKIN fall time f(CI) † CLKIN rise time r(CI) CLKIN low pulse duration, t...
  • Page 30 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 2.0 V 2.4 V (Min) (Min) 1.88 V 2.2 V 0.92 V 0.8 V (Max) (Max) 0.80 V 0.6 V (a) Input (b) Output Figure 5. Voltage Reference Levels...
  • Page 31 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 RS, INT, BIO, AND XF TIMING switching characteristics over recommended operating conditions (see Note 3 and 8) PARAMETER UNIT † CLKOUT1 low to reset state entered...
  • Page 32 TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER UNIT DX valid after CLKX rising edge (see Note 10) d(CH-DX) DX valid after FSX falling edge (TXM = 0, see Note 10)

  • Page 33: Eprom Programming

    TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 EPROM PROGRAMMING † absolute maximum ratings over specified temperature range (unless otherwise noted) ‡ Supply voltage range, V ............-- 0.6 V to 15 V Input voltage range on pins 24 and 25 .
  • Page 34 TMS320C25 50 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 † absolute maximum ratings over specified temperature range (unless otherwise noted) ‡ Supply voltage range, V ............-- 0.3 V to 7 V Input voltage range .
  • Page 35 TMS320C25 50 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 CLOCK CHARACTERISTICS AND TIMING The TMS320C25-50 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2, CLKIN. The frequency of CLKOUT1 is one-fourth the crystal fundamental frequency.
  • Page 36 TMS320C25 50 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 +5 V TMS320C25 crystal 10 k 74HC04 4.7 k CLKIN C = 20 pF 0.1 F 47 pF 74AS04 10 k (MHz) L, (H) crystal, TMS320C25 40.96 TMS320C25-50 51.20 TMS320E25 40.96 Figure 7.
  • Page 37 TMS320C25 50 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER UNIT STRB from CLKOUT (if STRB is present) Q -- 5 Q + 3 d(C1-S) CLKOUT2 to STRB (if STRB is present) -- 2 d(C2-S)
  • Page 38 TMS320C25 50 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 RS, INT, BIO, AND XF TIMING switching characteristics over recommended operating conditions (see Notes 3 and 16) PARAMETER UNIT † CLKOUT1 low to reset state entered d(RS) CLKOUT1 to IACK valid -- 5 d(IACK) XF valid before falling edge of STRB...
  • Page 39 TMS320C25 50 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER UNIT DX valid after CLKX rising edge (see Note 18) d(CH-DX) DX valid after falling edge (TXM = 0, see Note 18) d(FL-DX) FSX valid after CLKX raising edge (TXM = 1) d(CH-FS)
  • Page 40 TMS320C25 50 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 memory and peripheral interface timing TMS320C25 TMS320C25-50 UNIT PARAMETER Q -- 6 Q -- 5 Q + 3 d(C1-S) -- 6 -- 2 d(C2-S) Q -- 12 Q -- 11 su(A) Q -- 8 Q -- 4...

  • Page 41: Timing Diagrams

    SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 TIMING DIAGRAMS This section contains all the timing diagrams for the TMS320 second-generation devices. Refer to the top corner of page for the specific device. Timing measurements are referenced to and from a low voltage of 0.8 voltage and a high voltage of 2 volts, unless otherwise noted.

  • Page 42: Memory Read Timing

    TMS320 SECOND GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 memory read timing d(C1-S) CLKOUT1 d(C1-S) CLKOUT2 d(C2-S) d(C2-S) STRB w(SH) su(A) h(A) w(SL) A15-A0, BR, PS, DS Valid or IS a(A) d(SL-R) su(D)R READY h(SL-R) h(D)R D15-D0 Data In ...

  • Page 43: Memory Write Timing

    TMS320 SECOND GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 memory write timing CLKOUT1 CLKOUT2 STRB h(A) su(A) A15-A0, BR, PS, DS Valid or IS READY su(D)W h(D)W D15-D0 Data Out en(D) dis(D)  POST OFFICE BOX 1443...
  • Page 44 TMS320 SECOND GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 one wait-state memory access timing CLKOUT1 CLKOUT2 STRB h(C2H-R) A15-A0, BR, PS, DS, R/W or Valid h(C2H-R) d(C2H-R) d(C2H-R) READY d(M-R) h(M-R) h(M-R) d(M-R) D15-D0 (For Read Data In...

  • Page 45: Reset Timing

    TMS320 SECOND GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 reset timing CLKOUT1 su(IN) d(RS) su(IN) h(IN) w(RS) A15-A0 Valid Fetch Location 0 D15-D0 Valid Begin Program Execution STRB Control † Signals IACK Serial Port ‡ Control †...
  • Page 46 TMS320 SECOND GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 interrupt timing (TMS32020) CLKOUT1 STRB su(IN) h(IN) w(IN) INT2-INT0 d(IACK) f(IN) A15-A0 FETCH N FETCH N + 1 FETCH I FETCH I + 1 d(IACK) IACK interrupt timing (TMS320C25)
  • Page 47 TMS320 SECOND GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 serial port receive timing c(SCK) r(SCK) w(SCK) CLKR h(DR) f(SCK) h(FS) w(SCK) su(FS) su(DR) serial port transmit timing c(SCK) r(SCK) w(SCK) CLKX d(CH-DX) f(SCK) w(SCK) h(FS) (Input, TXM = 0)
  • Page 48 TMS32020 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 BIO timing CLKOUT1 STRB FETCH Branch Address FETCH Next Instruction FETCH A15-A0 BIOZ PC = N PC = N + 1 PC = N + 2 PC = N + 3 or Branch Address su(IN) h(IN)
  • Page 49 TMS320C25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 BIO timing CLKOUT1 STRB FETCH Branch Address FETCH Next Instruction FETCH A15-A0 BIOZ PC = N PC = N + 1 PC = N + 2 or Branch Address su(IN) h(IN) Valid external flag timing CLKOUT1...
  • Page 50 TMS32020 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 HOLD timing (part A) CLKOUT1 CLKOUT2 STRB † d(C2H-H) HOLD A15-A0 N + 1 N + 2 PS, DS, Valid Valid or IS dis(C1L-A) D15-D0 dis(AL-A) HOLDA d(C1L-AL) N + 1 FETCH N - - 1 Dummy...
  • Page 51 TMS32020 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 HOLD timing (part B) CLKOUT1 CLKOUT2 en(A-C1L) STRB † d(C2H-H) HOLD A15-A0 Valid Valid PS, DS, or IS d(HH-AH) D15-D0 HOLDA N + 2 N + 3 N /A N + 2 N + 3 FETCH Dead...
  • Page 52 TMS320C25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 HOLD timing (part A) CLKOUT1 CLKOUT2 STRB † d(C2H-H) HOLD A15-A0 N + 1 N + 2 PS, DS, Valid Valid or IS dis(C1L-A) D15-D0 dis(AL-A) HOLDA d(C1L-AL) N + 1 FETCH N - - 2 N - - 1...
  • Page 53 TMS320C25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 HOLD timing (part B) CLKOUT1 CLKOUT2 en(A-C1L) STRB † d(C2H-H) HOLD PS, DS, Valid or IS D15-D0 d(HH-AH) HOLDA A15-A0 N + 2 N + 2 N + 2 FETCH N + 1 EXECUTE †...
  • Page 54 TMS320 SECOND GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25 vs f and V vs f and V (CLKIN) (CLKIN) Normal Operating Mode Powerdown Mode = 5.50 V = 25  = 5.50 V = 5.25 V...

  • Page 55: Mechanical Data

    TMS320 SECOND GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 MECHANICAL DATA 68-pin GB grid array ceramic package (TMS32020, TMS320C25) 28,448 (1.120) 27,432 (1.080) Thermal Resistance Characteristics 17,02 (0.670) PARAMETER UNIT Junction-to-free-air C/W JA thermal resistance 28,448 (1.120) Junction-to-case 27,432 (1.080)
  • Page 56 TMS320C25 TMS320C25 50 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50) Seating Plane 1,27 (0.050) T.P. (see Note B) 0,25 (0.010) R Max 3 Places 24,33 (0.956) 24,13 (0.950) 23,62 (0.930) (see Note A) 23,11 (0.910) (At Seating Plane)
  • Page 57 TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 MECHANICAL DATA 68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only) This hermetically-sealed chip carrier package consists of a ceramic base, ceramic cap, and a 68-lead frame. Hermetic sealing is accomplished with glass. The FZ package is intended for both socket- or surface- mounting. Having a Sn/Pb ratio of 60/40, the tin/lead-coated leads do not require special cleaning or processing when being surface-mounted.
  • Page 58 TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 programming the TMS320E25 EPROM cell The TMS320E25 includes a 4K  16-bit EPROM, implemented from an industry-standard EPROM cell, to perform prototyping and early field testing and to achieve low-volume production. When used with a 4K-word masked-ROM TMS320C25, the TMS320E25 yields a high-volume, low-cost production as a result of more migration paths for data.
  • Page 59 TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Figure 9 shows the wiring conversion to program the TMS320E25 using the 28-pin pinout of the TMS27C64. The pin nomenclature table provides a description of the TMS27C64 pins. The code to be programmed into the device should be serial mode.
  • Page 60 TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 5 shows the programming levels required for programming, verifying and reading the EPROM cell. The paragraphs following the table describe the function of each programming level. Table 5. TMS320E25 Programming Mode Levels SIGNAL TMS320E25 TMS27C64...
  • Page 61 TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 program verify Programmed bits may be verified with V = 12.5 V when G = V , E = V , and PGM = V . Figure 11 shows the timing for the program and verify operation. Start Address = First Location...
  • Page 62 TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Program Verify A12-A0 Address Stable Address N + 1 Q8-Q1 Data In Stable HI-Z Data Out Valid CC + 1 Figure 11. Fast Programming Timing program inhibit Programming may be inhibited by maintaining a high level input on the E pin or PGM pin. read The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect bit) has not been programmed.
  • Page 63 TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 6. TMS320E25 Protect and Verify EPROM Mode Levels † SIGNAL TMS320E25 PIN TMS27C64 PIN ROM PROTECT PROTECT VERIFY 61,35 CC + 1 10, 27, 44 CLKIN Q8-Q1 18-11 11-13, 15-19 Q8 = PULSE Q8 = RBIT A12-A10...
  • Page 64 TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Start Program One Pulse of 3X-ms X = 0 Duration EPROM Protect Protect Verify Setup Setup Program One 1-ms Pulse Device Verify Device Failed RBIT Passed X = X + 1 X = 25? Protect Verify...
  • Page 65 TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Protect Verify CC + 1 HI-Z HI-Z HI-Z Figure 13. EPROM Protect Timing  POST OFFICE BOX 1443 HOUSTON, TEXAS 77001...
  • Page 66 INDEX TMS320 SECOND GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  POST OFFICE BOX 1443 HOUSTON, TEXAS 77001...
  • Page 67 ..... . . 21, 23-26 TMS320 family ......
  • Page 68 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples Drawing TMS320C25FNA NRND PLCC Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 @1986 TI &...
  • Page 69 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
  • Page 70 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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