ADLINK Technology Express-KL2 User Manual page 26

3.3.15. Power and System Management
Signal Pin #
PWRBTN# B12
SYS_RESET# B49
CB_RESET# B50
PWR_OK B24
SUS_STAT# B18
SUS_S3# A15
SUS_S4# A18
SUS_S5# A24
WAKE0# B66
WAKE1# B67
BATLOW# A27
20
Description
Power button to bring system out of S5 (soft off), active on
falling edge.
Reset button input. Active low request for module to reset
and reboot. May be falling edge sensitive. For situations
when SYS_RESET# is not able to reestablish control of the
system, PWR_OK or a power cycle may be used.
Reset output from module to Carrier Board. Active low.
Issued by module chipset and may result from a low
SYS_RESET# input, a low PWR_OK input, a VCC_12V
power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module
software.
Power OK from main power supply. A high value indicates
that the power is good. This signal can be used to hold off
Module startup to allow carrier based FPGAs or other
configurable devices time to be programmed.
Indicates imminent suspend operation; used to notify LPC
devices.
Indicates system is in Suspend to RAM state. Active-low
output. An inverted copy of SUS_S3# on the carrier board
(also known as "PS_ON") may be used to enable the non-
standby power on a typical ATX power supply.
Indicates system is in Suspend to Disk state. Active low
output.
Indicates system is in Soft Off state.
PCI Express wake up signal.
General purpose wake up signal. May be used to
implement wake-up on PS/2 keyboard or mouse activity.
Battery low input. This signal may be driven low by external
circuitry to signal that the system battery is low, or may be
used to signal some other external power-management
event.
I/O PU/PD Comment
I 3.3VSB PU 10k
3.3VSB
I 3.3VSB PU 10k
3.3VSB
O 3.3VSB PD 100K
I 3.3V PU 10k Should
3.3VSB have weak
pull up
O 3.3VSB
O 3.3VSB
O 3.3VSB
O 3.3VSB
I 3.3VSB PU 1K
3.3VSB
PU 1K Connect to
I 3.3VSB
3.3VSB WAKE 0#
I 3.3VSB PU 10k
3.3VSB
Pinouts and Signal Descriptions